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LY62L204916AGL-70SLT Datasheet(PDF) 9 Page - Lyontek Inc. |
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LY62L204916AGL-70SLT Datasheet(HTML) 9 Page - Lyontek Inc. |
9 / 12 page LY62L204916A Rev.1.2 2048K X 16 BIT LOW POWER CMOS SRAM Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 8 ® DATA RETENTION CHARACTERISTICS PARAMETER SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT VCC for Data Retention VDR CE#≧VCC - 0.2V or CE2≦0.2V 1.2 - 3.6 V Data Retention Current IDR VCC = 1.2V CE# V ≧ CC-0.2V or CE2≦0.2V other pins at 0.2V or VCC-0.2V -SL -SLI 25℃ - 6 16 µA 40℃ - 6 16 µA -SL - 6 60 µA -SLI - 6 80 µA Chip Disable to Data Retention Time tCDR See Data Retention Waveforms (below) 0 - - ns Recovery Time tR tRC* - - ns tRC* = Read Cycle Time DATA RETENTION WAVEFORM Low Vcc Data Retention Waveform (1) (CE# controlled) Vcc CE# VDR ≧ 1.2V CE# V ≧ cc-0.2V Vcc(min.) VIH tR tCDR VIH Vcc(min.) Low Vcc Data Retention Waveform (2) (CE2 controlled) Vcc CE2 VDR ≧ 1.2V CE2 ≦ 0.2V Vcc(min.) VIL tR tCDR VIL Vcc(min.) Low Vcc Data Retention Waveform (3) (LB#, UB# controlled) Vcc LB#,UB# VDR ≧ 1.2V LB#,UB# V ≧ cc-0.2V Vcc(min.) VIH tR tCDR VIH Vcc(min.) |
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