LY611024

Rev. 1.6

128K X 8 BIT HIGH SPEED CMOS SRAM

5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.

TEL: 886-3-6668838

FAX: 886-3-6668836

1

®

FEATURES

Fast access time : 12/15ns

Low power consumption:

Operating current : 50/40mA (TYP.)

Standby current : 1mA (TYP.)

2

μA (TYP.) LL -version

Single 4.5V ~ 5.5V power supply

All inputs and outputs TTL compatible

Fully static operation

Tri-state output

Data retention voltage : 2.0V (MIN.)

Green package available

Package : 32-pin 300 mil SOJ

32-pin 8mm x 20mm TSOP-I

32-pin 8mm x 13.4mm STSOP

GENERAL DESCRIPTION

The LY611024 is a 1,048,576-bit low power CMOS

static random access memory organized as 131,072

words by 8 bits. It is fabricated using very high

performance, high reliability CMOS technology. Its

standby current is stable within the range of

operating temperature.

The LY611024 is well designed for very high speed

system applications, and particularly well suited for

battery back-up nonvolatile memory application.

The LY611024 operates from a single power

supply of 4.5V ~ 5.5V and all inputs and outputs are

fully TTL compatible

PRODUCT FAMILY

Product

Family

Operating

Temperature

Vcc Range

Speed

Power Dissipation

Operating(Icc,TYP.)

LY611024

0 ~ 70℃

4.5 ~ 5.5V

12/15ns

1mA

50/40mA

LY611024(E)

-20 ~ 80℃

4.5 ~ 5.5V

12/15ns

1mA

50/40mA

LY611024(I)

-40 ~ 85℃

4.5 ~ 5.5V

12/15ns

1mA

50/40mA

LY611024(LL)

0 ~ 70℃

4.5 ~ 5.5V

12/15ns

2µA

50/40mA

LY611024(LLE)

-20 ~ 80℃

4.5 ~ 5.5V

12/15ns

2µA

50/40mA

LY611024(LLI)

-40 ~ 85℃

4.5 ~ 5.5V

12/15ns

2µA

50/40mA

FUNCTIONAL BLOCK DIAGRAM

DECODER

I/O DATA

CIRCUIT

CONTROL

CIRCUIT

128Kx8

MEMORY ARRAY

COLUMN I/O

A0-A16

Vcc

Vss

DQ0-DQ7

CE#

WE#

OE#

CE2

PIN DESCRIPTION

SYMBOL

DESCRIPTION

A0 - A16

Address Inputs

DQ0 – DQ7

Data Inputs/Outputs

CE#, CE2

Chip Enable Inputs

WE#

Write Enable Input

OE#

Output Enable Input

Power Supply

Ground

NC

No Connection