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AD725-EB Datasheet(PDF) 8 Page - Analog Devices |
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AD725-EB Datasheet(HTML) 8 Page - Analog Devices |
8 / 20 page REV. 0 –8– AD725 Following the dc clamps, the RGB inputs are buffered and split into two signal paths for constructing the luminance and chrominance outputs. Luminance Signal Path The luminance path begins with the luma (Y) matrix. This matrix combines the RGB inputs to form the brightness infor- mation in the output video. The inputs are combined by the standard transformation Y = 0.299 × R + 0.587 × G + 0.114 × B This equation describes the sensitivity of the human eye to the individual component colors, combining them into one value of brightness. The equation is balanced so that full-scale RGB inputs give a full-scale Y output. Following the luma matrix, the composite sync is added. The user-supplied sync (from the HSYNC and VSYNC inputs) is latched into the AD725 at half the master clock rate, gating a sync pulse into the luminance signal. With the exception of transitioning on the clock edges, the output sync timing will be in the same format as the input sync timing. The output sync level will depend on the encoding standard, 286 mV (40 IRE) for NTSC and 300 mV for PAL (voltages at the pin will be twice these levels). In order to be time-aligned with the filtered chrominance signal path, the luma signal must be delayed before it is output. The AD725 uses a sampled delay line to achieve this delay. Following the luma matrix and prior to this delay line, a prefilter removes higher frequencies from the luma signal to prevent aliasing by the sampled delay line. This three-pole Bessel low-pass filter has a –3 dB frequency of 4.85 MHz for NTSC, 6 MHz for PAL. After the luma prefilter, the bandlimited luma signal is sampled onto a set of capacitors at twice the master reference clock rate. After an appropriate delay, the data is read off the delay line, reconstructing the luma signal. The 8FSC oversampling of this delay line limits the amount of jitter in the reconstructed sync output. The clocks driving the delay line are reset once per video line during the burst flag. The output of the luma path will remain unchanged during this period and will not respond to changing RGB inputs. 4FSC NTSC/PAL HSYNC VSYNC BURST NTSC/PAL FSC 90 C FSC 0 C 4FSC FSC 90 C/270 C CSYNC CSYNC RED GREEN BLUE CSYNC Y U V BALANCED MODULATORS NTSC/PAL X2 X2 X2 LUMINANCE OUTPUT COMPOSITE OUTPUT CHROMINANCE OUTPUT CLOCK AT 8FSC SYNC SEPARATOR QUADRATURE +4 DECODER BURST 3-POLE LP PRE- FILTER 4-POLE LPF 4-POLE LPF 180 C (PAL ONLY) RGB-TO-YUV ENCODING MATRIX SAMPLED- DATA DELAY LINE 4-POLE LPF 2-POLE LP POST- FILTER LUMINANCE TRAP 4FSC CLOCK V CLAMP U CLAMP DC CLAMP DC CLAMP DC CLAMP XNOR POWER AND GROUNDS +5V +5V AGND DGND LOGIC ANALOG ANALOG LOGIC NOTE: THE LUMINANCE, COMPOSITE AND CHROMINANCE OUTPUTS ARE AT TWICE NORMAL LEVELS FOR DRIVING 75 REVERSE-TERMINATED LINES. Figure 17. Functional Block Diagram THEORY OF OPERATION The AD725 is a predominantly analog design, with digital logic control of timing. This timing logic is driven by a external fre- quency reference at four times the color subcarrier frequency, input into the 4FSC pin of the AD725. This frequency should be 14.318 180 MHz for NTSC encoding, and 17.734 475 MHz for PAL encoding. The 4FSC input accepts standard TTL logic levels. The duty cycle of this input clock is not critical, but a fast- edged clock should be used to prevent excessive jitter in the timing. The AD725 accepts two common sync standards, composite sync or separate horizontal and vertical syncs. To use an exter- nal composite sync, a logic high signal is input to the VSYNC pin and the composite sync is input to the HSYNC pin. If sepa- rate horizontal and vertical syncs are available, the horizontal sync can be input to the HSYNC pin and vertical sync to the VSYNC pin. Internally, the device XNORs the two sync inputs to combine them into one negative-going composite sync. The AD725 detects the falling sync pulse edges, and times their width. A sync pulse of standard horizontal width will cause the insertion of a colorburst vector into the chroma modulators at the proper time. A sync pulse outside the detection range will cause suppression of the color burst, and the device will enter its vertical blanking mode. During this mode, the on-chip RC time constants are verified using the input frequency reference, and the filter cutoff frequencies are retuned as needed. The component color inputs, RIN, GIN and BIN, receive ana- log signals specifying the desired active video output. The full- scale range of the inputs is 0.714 mV (for either NTSC or PAL operation). External black level is not important as these inputs are terminated externally, and then ac coupled to the AD725. The AD725 contains on-chip RGB input clamps to restore the dc level on-chip to match its single supply signal path. This dc restore timing is coincident with the burst flag, starting approxi- mately 5.5 µs after the falling sync edge and lasting for 2.5 µs. During this time, the device should be driven with a black input. |
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