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74LVC821AD Datasheet(PDF) 11 Page - NXP Semiconductors |
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74LVC821AD Datasheet(HTML) 11 Page - NXP Semiconductors |
11 / 20 page 74LVC821A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 4 — 23 November 2012 11 of 20 NXP Semiconductors 74LVC821A 10-bit D-type flip-flop; 5 V tolerance; positive-edge trigger; 3-state Measurement points are given in Table 8. VOL and VOH are the typical output voltage levels that occur with the output load. Fig 9. 3-state enable and disable times mgu775 tPLZ tPHZ outputs disabled outputs enabled VY VX outputs enabled Qn output LOW-to-OFF OFF-to-LOW Qn output HIGH-to-OFF OFF-to-HIGH OE input VI VOL VOH VCC VM VM GND GND tPZL tPZH VM VM Table 8. Measurement points Supply voltage Input Output VCC VI VM VM VX VY 1.2 V VCC 0.5 V CC 0.5 V CC VOL + 0.15 V VOH 0.15 V 1.65 V to 1.95 V VCC 0.5 V CC 0.5 V CC VOL + 0.15 V VOH 0.15 V 2.3 V to 2.7 V VCC 0.5 V CC 0.5 V CC VOL + 0.15 V VOH 0.15 V 2.7 V 2.7 V 1.5 V 1.5 V VOL + 0.3 V VOH 0.3 V 3.0 V to 3.6 V 2.7 V 1.5 V 1.5 V VOL + 0.3 V VOH 0.3 V |
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