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74LVC821ADB Datasheet(PDF) 6 Page - NXP Semiconductors |
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74LVC821ADB Datasheet(HTML) 6 Page - NXP Semiconductors |
6 / 20 page 74LVC821A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 4 — 23 November 2012 6 of 20 NXP Semiconductors 74LVC821A 10-bit D-type flip-flop; 5 V tolerance; positive-edge trigger; 3-state 6. Functional description [1] H = HIGH voltage level h = HIGH voltage level one set-up time before the LOW-to-HIGH CP transition L = LOW voltage level l = LOW voltage level one set-up time before the LOW-to-HIGH CP transition Z = high-impedance OFF-state = LOW-to-HIGH clock transition X = don’t care NC = no change 7. Limiting values [1] The minimum input voltage ratings may be exceeded if the input current ratings are observed. [2] The output voltage ratings may be exceeded if the output current ratings are observed. [3] For SO24 package: above 70 C derate linearly with 8 mW/K. For SSOP24 and TSSOP24 packages: above 60 C derate linearly with 5.5 mW/K. For DHVQFN24 package: above 60 C derate linearly with 4.5 mW/K. Table 3. Function table[1] Operating mode Input Internal flip-flops Output OE CP Dn Qn Load and read register L IL L L hH H Load register and disable outputs H IL Z H hH Z Hold L H or L X NC NC Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit VCC supply voltage 0.5 +6.5 V IIK input clamping current VI <0 V 50 - mA VI input voltage [1] 0.5 +6.5 V IOK output clamping current VO >VCC or VO <0 V - 50 mA VO output voltage HIGH or LOW state [2] 0.5 VCC + 0.5 V 3-state [2] 0.5 +6.5 V IO output current VO =0 V to VCC - 50 mA ICC supply current - 100 mA IGND ground current 100 - mA Tstg storage temperature 65 +150 C Ptot total power dissipation Tamb = 40 C to +125 C [3] -500 mW |
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