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MP6400DG-30 Datasheet(PDF) 4 Page - Monolithic Power Systems

Part # MP6400DG-30
Description  Low Quiescent Current Programmable-Delay Supervisory Circuit
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Manufacturer  MPS [Monolithic Power Systems]
Direct Link  http://www.monolithicpower.com
Logo MPS - Monolithic Power Systems

MP6400DG-30 Datasheet(HTML) 4 Page - Monolithic Power Systems

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MP6400 -- LOW QUIESCENT CURRENT PROGRAMMABLE-DELAY SUPERVISORY CIRCUIT
MP6400 Rev. 1.0
www.MonolithicPower.com
4
9/7/2012
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
TM
ELECTRICAL CHARACTERISTICS
1.8V≤VCC≤6V, R3 = 100kΩ, C3 = 47pF, TA= -40°C to +85°C, Typical values are at TA=+25°C, unless
otherwise noted.
Parameters
Symbol Condition
Min
Typ
Max
Units
Input Supply Range
VCC
1.8
6
V
VCC = 3.3V,
R E S E T
not
asserted.
M R
,
R E S E T
,
CDELAY open
1.6
3.5
µA
Supply Current
(current into VCC pin)
ICC
VCC = 6V,
R E S E T
not
asserted.
M R
,
R E S E T
,
CDELAY open
1.85
12
µA
1.3V ≤ VCC < 1.8V,
IOL = 0.4mA
0.3
V
Low-level Output Voltage
VOL
1.8V ≤ VCC ≤ 6V,
IOL = 1.0mA
0.4
V
Power-up Reset Voltage
(5)
VOL (max) = 0.2V,
R E S E T
I
1 5 u A
=
Trise(Vcc)≥15µs/V
0.8
V
Negative-going Input Threshold
Accuracy
VIT
VSENSE falling slowly
±1.0
±2.0
%
Hysteresis on VIT Pin
VHYS
1.5
3.5
VIT%
M R
Internal Pull-up Resistance
M R
R
50
110
kΩ
MP6400DJ-01
VSENSE = VIT
-25
+25
nA
Input Current at SENSE Pin
ISENSE
Fixed versions
VSENSE = 6V
2.4
µA
R E S E T
Leakage Current
R E S E T
V
= 6V,
R E S E T
not
asserted
300
nA
M R
Logic Low Input
VIL
0.25VCC
V
M R
Logic High Input
VIH
0.7VCC
V
SENSE
Maximum
Transient
Duration
tw
VIH = 1.05 VIT,
VIL = 0.95 VIT
17.5
µs
CDELAY = Open
15
24
34
ms
CDELAY = VCC
(6)
230
380
530
ms
CDELAY = 150pF
1.3
2.1
3
ms
R E S E T
Delay Time
td
CDELAY = 10nF
(6)
61
102
142
ms
M R
to
R E S E T
Propagation Delay
tpHL1
VIH = 0.7 VCC,
VIL = 0.25 VCC
160
ns
High to Low Level
R E S E T
Delay,
SENSE to
R E S E T
tpHL2
VIH = 1.05 VIT,
VIL = 0.95 VIT
17.5
µs
Note:
5) The lowest supply voltage (VCC) at which
R E S E T
becomes active.
6) Guaranteed by design.


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