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119-7054-XX Datasheet(PDF) 9 Page - List of Unclassifed Manufacturers |
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119-7054-XX Datasheet(HTML) 9 Page - List of Unclassifed Manufacturers |
9 / 22 page State acquisition with P6800 or P6900 series probes Channel configurations Full channel Half channel Quarter channel 235 MHz 0 MHz / 450 Mb/s or 470 Mb/s (DDR) 450 MHz / 900 Mb/s 450 MHz Optional 800 MHz / 800 Mb/s or 900 Mb/s (DDR) 625 MHz / 1.25 Gb/s State record length with Time stamps (Quarter/Half/Full channels) 8/4/2 Mb, 32/16/8 Mb, 128/64/32 Mb, 512/256/128 Mb per channel Setup and Hold time selection range From 16 ns before, to 8 ns after clock edge in 125 ps increments. Range may be shifted towards the setup region by 0 ns [+8, -8] ns, 4 ns [+12, -4] ns, or 8 ns [+16, 0] ns Setup and Hold window All channels 625 ps typical Single channel 500 ps typical Minimum clock pulse width 500 ps (P6960, P6962, P6964, P6980, P6982, P6860), 700 ps (P6910) Active clock pulse separation 400 ps Demux channel selection Channels can be demultiplexed to other channels through user interface with 8-channel granularity. Source synchronous clocking Up to four "Fast Latches" per module (20 max per 5-way merge) to strobe source-synchronous buses into TLA7ACx modules. Four sets of any predefined "Fast Latches" may be combined with qualification data and data pipelining to store four independent source-synchronous data buses. Two "Fast Latches" may be combined to address DDR applications. Timing acquisition (with P6800 or P6900 probes) MagniVu™ timing 125 ps max, adjustments to 250 ps, 500 ps, 1 ns, and 2 ns MagniVu timing record length 16 Kb per channel, with adjustable trigger position Deep timing resolution (Quarter/ Half/Full channels) 500 ps / 1 ns / 2 ns to 50 ms Deep timing resolution with glitch storage enabled 4 ns to 50 ms Deep timing record length (Quarter/Half/Full channels with time stamps and with or without transitional storage) 8/4/2 Mb, 32/16/8 Mb,128/64/32 Mb, 512/256/128 Mb per channel Deep timing record length with glitch storage enabled Half of default main memory depth Channel-to-channel skew 300 ps typical Minimum recognizable pulse/glitch width (single channel) 500 ps (P6960, P6962, P6964, P6980, P6982, P6860), 750 ps (P6910) Minimum detectable Setup/Hold violation 250 ps Minimum recognizable multichannel Trigger event Sample period + channel-to-channel skew Tektronix Logic Analyzers – TLA7000 Series www.tektronix.com 9 |
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