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24LC21IP Datasheet(PDF) 5 Page - Microchip Technology

Part # 24LC21IP
Description  1K 2.5V Dual Mode I2C Serial EEPROM
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

24LC21IP Datasheet(HTML) 5 Page - Microchip Technology

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 2004 Microchip Technology Inc.
DS21095J-page 5
24LC21
3.0
BIDIRECTIONAL MODE
The 24LC21 can be switched into the Bidirectional
mode (see Figure 3-1) by applying a valid high-to-low
transition on the Bidirectional mode clock (SCL). When
the device has been switched into the Bidirectional
mode, the VCLK input is disregarded, with the exception
that a logic high level is required to enable write capa-
bility. This mode supports a two wire bidirectional data
transmission protocol. In this protocol, a device that
sends data on the bus is defined to be the transmitter,
and a device that receives data from the bus is defined
to be the receiver. The bus must be controlled by a
master device that generates the Bidirectional mode
clock (SCL), controls access to the bus and generates
the Start and Stop conditions, while the 24LC21 acts as
the slave. Both master and slave can operate as
transmitter
or
receiver,
but
the
master
device
determines which mode is activated.
3.1
Bidirectional Mode Bus
Characteristics
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.
Accordingly, the following bus conditions have been
defined (see Figure 3-2).
3.1.1
BUS NOT BUSY (A)
Both data and clock lines remain high.
3.1.2
START DATA TRANSFER (B)
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
3.1.3
STOP DATA TRANSFER (C)
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must be ended with a Stop condition.
FIGURE 3-1:
MODE TRANSITION
FIGURE 3-2:
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
SCL
SDA
VCLK
Bidirectional mode
TVHZ
Transmit-only mode
(A)
(B)
(D)
(D)
(A)
(C)
Start
Condition
Address or
Acknowledge
Valid
Data
Allowed
to Change
Stop
Condition
SCL
SDA


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