AD9432BSTZ-1051 datasheet(2/16 Pages) AD

Part #	AD9432BSTZ-1051

Description	12-Bit, 80 MSPS/105 MSPS ADC

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Manufacturer	AD [Analog Devices]

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REV. E

–2–

AD9432–SPECIFICATIONS

Test

AD9432BST/BSQ-80

AD9432BST/BSQ-105

Parameter

Temp

Level

Min

Typ

Max

Min

Typ

Max

Unit

RESOLUTION

12

Bits

DC ACCURACY

Differential Nonlinearity

25

°C

I

–0.75

±0.25

+0.75

–0.75

±0.25

+0.75

LSB

Full

VI

–1.0

±0.5

+1.0

–1.0

±0.5

+1.0

LSB

Integral Nonlinearity

25

°C

I

–1.0

±0.5

+1.0

–1.0

±0.5

+1.0

LSB

Full

VI

–1.5

±1.0

+1.5

–1.5

±1.0

+1.5

LSB

No Missing Codes

Full

VI

Guaranteed

Gain Error

1

25

°C

I

–5

+2

+7

–5

+2

+7

% FS

Gain Tempco

1

Full

V

150

ppm/

°C

ANALOG INPUT

Input Voltage Range (AIN–

AIN)

Full

V

±1.0

V

Common-Mode Voltage

Full

V

3.0

V

Input Offset Voltage

Full

VI

–5

±0+5

–5

±0+5

mV

Input Resistance

Full

VI

2

3

4

2

3

4

k

Ω

Input Capacitance

25

°CV

4

pF

Analog Bandwidth, Full Power

25

°C

V

500

MHz

ANALOG REFERENCE

Output Voltage

Full

VI

2.4

2.5

2.6

2.4

2.5

2.6

V

Tempco

Full

V

50

ppm/

°C

Input Bias Current

Full

VI

15

50

15

50

µΑ

SWITCHING PERFORMANCE

Maximum Conversion Rate

Full

VI

80

105

MSPS

Minimum Conversion Rate

Full

IV

1

MSPS

Encode Pulsewidth High (tEH)25

°C

IV

4.0

6.2

4.0

4.8

ns

Encode Pulsewidth Low (tEL)25

°C

IV

4.0

6.2

4.0

4.8

ns

Aperture Delay (tA)25

°C

V

2.0

ns

Aperture Uncertainty (Jitter)

25

°C

V

0.25

ps rms

Output Valid Time (tV)

2

Full

VI

3.0

5.3

3.0

5.3

ns

Output Propagation Delay (tPD)

2

Full

VI

5.5

8.0

5.5

8.0

ns

Output Rise Time (tR)

2

Full

V

2.1

ns

Output Fall Time (tF)

Full

V

1.9

ns

Out-of-Range Recovery Time

25

°CV

2

ns

Transient Response Time

25

°CV

2

ns

Latency

Full

IV

10

Cycles

DIGITAL INPUTS

Encode Input Common Mode

Full

V

1.6

V

Differential Input (ENC–

ENC)

Full

V

750

mV

Single-Ended

Logic “1” Voltage

Full

IV

2.0

V

Logic “0” Voltage

Full

IV

0.8

V

Input Resistance

Full

VI

3

5

8

3

5

8

k

Ω

Input Capacitance

25

°C

V

4.5

pF

DIGITAL OUTPUTS

Logic “1” Voltage (VDD = 3.3 V)

Full

VI

VDD – 0.05

V

Logic “0” Voltage (VDD = 3.3 V)

Full

VI

0.05

V

Output Coding

Two’s Complement

POWER SUPPLY

Power Dissipation

3

Full

VI

790

1000

850

1100

mW

Power Supply Rejection Ratio (PSRR) 25

°C

I

–5

+0.5

+5

–5

+0.5

+5

mV/V

IVCC

Full

VI

158

200

170

220

mA

IVDD

Full

VI

9.5

12.2

12.5

16

mA

(VDD = 3.3 V, VCC = 5.0 V; external reference; differential encode input, unless

otherwise noted.)

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