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AD9516-5BCPZ Datasheet(PDF) 10 Page - Analog Devices |
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AD9516-5BCPZ Datasheet(HTML) 10 Page - Analog Devices |
10 / 76 page AD9516-5 Rev. A | Page 10 of 76 SERIAL CONTROL PORT Table 10. Parameter Min Typ Max Unit Test Conditions/Comments CS (INPUT) CS has an internal 30 kΩ pull-up resistor Input Logic 1 Voltage 2.0 V Input Logic 0 Voltage 0.8 V Input Logic 1 Current 3 μA Input Logic 0 Current 110 μA Input Capacitance 2 pF SCLK (INPUT) SCLK has an internal 30 kΩ pull-down resistor Input Logic 1 Voltage 2.0 V Input Logic 0 Voltage 0.8 V Input Logic 1 Current 110 μA Input Logic 0 Current 1 μA Input Capacitance 2 pF SDIO (WHEN INPUT) Input Logic 1 Voltage 2.0 V Input Logic 0 Voltage 0.8 V Input Logic 1 Current 10 nA Input Logic 0 Current 20 nA Input Capacitance 2 pF SDIO, SDO (OUTPUTS) Output Logic 1 Voltage 2.7 V Output Logic 0 Voltage 0.4 V TIMING Clock Rate (SCLK, 1/tSCLK) 25 MHz Pulse Width High, tHIGH 16 ns Pulse Width Low, tLOW 16 ns SDIO to SCLK Setup, tDS 2 ns SCLK to SDIO Hold, tDH 1.1 ns SCLK to Valid SDIO and SDO, tDV 8 ns CS to SCLK Setup and Hold, tS, tH 2 ns CS Minimum Pulse Width High, tPWH 3 ns PD, RESET, AND SYNC PINS Table 11. Parameter Min Typ Max Unit Test Conditions/Comments INPUT CHARACTERISTICS Each of these pins has an internal 30 kΩ pull-up resistor Logic 1 Voltage 2.0 V Logic 0 Voltage 0.8 V Logic 1 Current 110 μA Logic 0 Current 1 μA Capacitance 2 pF RESET TIMING Pulse Width Low 50 ns SYNC TIMING Pulse Width Low 1.5 High speed clock cycles High speed clock is CLK input signal |
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