AD9549APCBZ datasheet(5/76 Pages) AD

Part #	AD9549APCBZ

Description	Dual Input Network Clock Generator/Synchronizer

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Manufacturer	AD [Analog Devices]

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AD9549

Rev. D | Page 5 of 76

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

SYSTEM CLOCK INPUT

System clock inputs should always be ac-

coupled (both single-ended and differential)

SYSCLK PLL Bypassed

Input Capacitance

1.5

pF

Single-ended, each pin

Input Resistance

2.4

2.6

2.8

kΩ

Differential

Internally Generated DC Bias Voltage2

0.93

1.17

1.38

V

Differential Input Voltage Swing3

632

mV p-p

0 dBm into 50 Ω

SYSCLK PLL Enabled

Input Capacitance

3

pF

Single-ended, each pin

Input Resistance

2.4

2.6

2.8

kΩ

Differential

Internally Generated DC Bias Voltage2

0.93

1.17

1.38

V

Differential Input Voltage Swing3

632

mV p-p

0 dBm into 50 Ω

Crystal Resonator with SYSCLK PLL Enabled

Motional Resistance

9

100

Ω

25 MHz, 3.2 mm × 2.5 mm AT cut

CLOCK OUTPUT DRIVERS

HSTL Output Driver

Differential Output Voltage Swing

1080

1280

1480

mV

Output driver static; see

Figure 12 for output

swing vs. frequency

Common-Mode Output Voltage2

0.7

0.88

1.06

V

CMOS Output Driver

Output driver static; see

Figure 13 and

Figure 14 for output swing vs. frequency

Output Voltage High (VOH)

2.7

V

IOH = 1 mA, (Pin 37) = 3.3 V

Output Voltage Low (VOL)

0.4

V

IOL = 1 mA, (Pin 37) = 3.3 V

Output Voltage High (VOH)

1.4

V

IOH = 1 mA, (Pin 37) = 1.8 V

Output Voltage Low (VOL)

0.4

V

IOL = 1 mA, (Pin 37) = 1.8 V

TOTAL POWER DISSIPATION

All Blocks Running4

1060

1310

mW

Worst case over supply, temperature, process

Power-Down Mode

24

70

mW

Using either the power-down and enable

register (Register 0x0010) or the PWRDOWN pin

Digital Power-Down Mode

565

713

mW

Default with SYSCLK PLL Enabled

955

mW

After reset or power-up with fS = 1 GHz,

S4 = 0, S1 to S3 = 1, fSYSCLK = 25 MHz

Default with SYSCLK PLL Disabled

945

1115

mW

After reset or power-up with fS = 1 GHz,

S1 to S4 = 1

With REFA or REFB Power-Down

1105

mW

One reference still powered up

With HSTL Clock Driver Power-Down

1095

mW

With CMOS Clock Driver Power-Down

1107

mW

1 Must be

≤0 V relative to AVDD3 (Pin 14) and ≥0 V relative to AVSS (Pin 33, Pin 43).

2 Relative to AVSS (Pin 33, Pin 43).

3 Must be

≤0 V relative to AVDD (Pin 36) and ≥0 V relative to AVSS (Pin 33, Pin 43).

4 Typical measurement done with only REFA and HSTL output doubler turned off.

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