ZSSC3036

Low-Power 16-Bit Sensor Signal Conditioner IC

Data Sheet

May 28, 2013

© 2013 Zentrum Mikroelektronik Dresden AG

— Rev. 1.20

All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without

the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice.

8 of 49

A dynamic power-on-reset circuit is implemented in order to achieve minimum current consumption in idle mode.

The VDD low level and the subsequent rise time and VDD rising slope must meet the requirements in Table 1.1 to

guarantee an overall IC reset: lower VDD low levels allow slower rising of the subsequent on-ramp of VDD. Other

combinations might also be possible. For example, the reset trigger can be influenced by increasing the power-

down time and lowering the VDD rising slope requirement.

Table 1.3

Requirements for VDD Power-on Reset

PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

Power Down Time (duration of VDD Low Level)

3

-

-

µs

VDD Low Level

0

-

0.2

V

VDD Rising Slope

10

-

-

V/ms

1.3.

Electrical Parameters

All parameter values are valid only under the specified operating conditions. All voltages are referenced to Vss.

Table 1.4

Electrical Parameters

Note: See important table notes at the end of the table.

Parameter

Symbol

Conditions/Comments

Min

Typ

Max

Unit

Supply

Bridge Supply Voltage,

ADC Reference Voltage

Internally generated

1.60

1.67

1.74

V

Current Consumption

Active State, average

900

1500

µA

Sleep State, idle current,

 85°C

20

250

nA

Sleep State, idle current,

110°C

50

950

nA

Power Supply Rejection

(see section 1.4)

17

dB

32

dB

Memory Program Voltage

Required voltage level at VDD pin

2.9

3.6

V

Mean Program Current

Mean current consumption during

MTP programming cycle at VDD

6

mA

Peak Program Current

MTP Program at VDD-pin,

dynamic switch-on current draw

20

mA