REV. B

–8–

ADP3334

Current and thermal limit protections are intended to protect

the device against accidental overload conditions. For normal

operation, device power dissipation should be externally limited

so that junction temperatures will not exceed 150°C.

Calculating Junction Temperature

Device power dissipation is calculated as follows:

PV

V

I

V

I

DINOUT

LOAD

IN

GND

=-

()

+

()

(8)

PmA

mA

mW

D

=-

()

+

52 8 400

5 0 4

900

..

(9)

As an example, the proprietary package used in the ADP3334

has a thermal resistance of 86.6°C/W, significantly lower than

a standard SOIC-8 package. Assuming a 4-layer board, the

junction temperature rise above ambient temperature will be

approximately equal to:

DT= .

W

C W

C

A

J

0 900

86 6

77 9

¥

∞

=

∞

./

.

(10)

To limit the maximum junction temperature to 150°C, maxi-

mum allowable ambient temperature will be:

TC / W

C

AMAX

=

∞ -

∞

=

∞

150

77 9

72 1

C

..

(11)

The maximum power dissipation versus ambient temperature

for each package is shown in Figure 5.

AMBIENT TEMPERATURE – C

3.5

–20

0

20

406080

2.5

1.5

1.0

0.5

0

3.0

2.0

158 C/W MSOP

220 C/W MSOP

122 C/W SOIC

86 C/W SOIC

62 C/W LFCSP

48 C/W LFCSP

Figure 5. Power Derating Curve

Printed Circuit Board Layout Consideration

All surface-mount packages rely on the traces of the PC board

to conduct heat away from the package.

In standard packages, the dominant component of the heat

resistance path is the plastic between the die attach pad and the

individual leads. In typical thermally enhanced packages, one or

more of the leads are fused to the die attach pad, significantly

decreasing this component. To make the improvement mean-

ingful, however, a significant copper area on the PCB must be

attached to these fused pins.

As an example, the patented thermal coastline lead frame design

of the ADP3334 uniformly minimizes the value of the dominant

portion of the thermal resistance. It ensures that heat is con-

ducted away by all pins of the package. This yields a very low

86.6°C/W thermal resistance for the SOIC-8 package, without

any special board layout requirements, relying only on the normal

traces connected to the leads. This yields a 15% improvement in

heat dissipation capability as compared to a standard SOIC-8

package. The thermal resistance can be decreased by an addi-

tional 10% by attaching a few square centimeters of copper area

to the IN or OUT pins of the ADP3334 package.

It is not recommended to use solder mask or silkscreen on the

PCB traces adjacent to the ADP3334’s pins since it will increase

the junction-to-ambient thermal resistance of the package.

0.50

2x VIAS, 0.250

35µm PLATING

3.36

0.90

1.80

2.36

1.90

1.40

0.30

0.73

Figure 6. 3 mm x 3 mm LFCSP Pad Pattern

(Dimensions shown in millimeters)

LFCSP Layout Considerations

The LFCSP package has an exposed die paddle on the bottom,

which efficiently conducts heat to the PCB. In order to achieve

the optimum performance from the LFCSP package, special

consideration must be given to the layout of the PCB. Use the

following layout guidelines for the LFCSP package.

1. The pad pattern is given in Figure 6. The pad dimension

should be followed closely for reliable solder joints while

maintaining reasonable clearances to prevent solder bridging.

2. The thermal pad of the LFCSP package provides a low ther-

mal impedance path (approximately 20°C/W) to the PCB.

Therefore the PCB must be properly designed to effectively

conduct the heat away from the package. This is achieved by

adding thermal vias to the PCB, which provide a thermal

path to the inner or bottom layers. See Figure 5 for the rec-

ommended via pattern. Note that the via diameter is small to

prevent the solder from flowing through the via and leaving

voids in the thermal pad solder joint.

Note that the thermal pad is attached to the die substrate, so

the thermal planes that the vias attach the package to must

nect the thermal pad to ground.