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ADSP-2186LKST-115R3 Datasheet(PDF) 11 Page - Analog Devices |
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ADSP-2186LKST-115R3 Datasheet(HTML) 11 Page - Analog Devices |
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11 / 48 page  ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L Rev. C | Page 11 of 48 | January 2008 See Figure 9 and Figure 10 for illustration of the programmable flag and composite control register and the system control register. Byte Memory Select The ADSP-218xL’s BMS disable feature combined with the CMS pin allows use of multiple memories in the byte memory space. For example, an EPROM could be attached to the BMS select, and a flash memory could be connected to CMS. Because at reset BMS is enabled, the EPROM would be used for booting. After booting, software could disable BMS and set the CMS sig- nal to respond to BMS, enabling the flash memory. Byte Memory The byte memory space is a bidirectional, 8-bit-wide, external memory space used to store programs and data. Byte memory is accessed using the BDMA feature. The byte memory space consists of 256 pages, each of which is 16K 8bits. The byte memory space on the ADSP-218xL series supports read and write operations as well as four different data formats. The byte memory uses data bits 15–8 for data. The byte mem- ory uses data bits 23–16 and address bits 13–0 to create a 22-bit address. This allows up to a 4 megabit 8 (32 megabit) ROM or RAM to be used without glue logic. All byte memory accesses are timed by the BMWAIT register. Byte Memory DMA (BDMA, Full Memory Mode) The byte memory DMA controller (Figure 11) allows loading and storing of program instructions and data using the byte memory space. The BDMA circuit is able to access the byte memory space while the processor is operating normally and steals only one DSP cycle per 8-, 16-, or 24-bit word transferred. The BDMA circuit supports four different data formats that are selected by the BTYPE register field. The appropriate number of 8-bit accesses are done from the byte memory space to build the word size selected. Table 7 shows the data formats supported by the BDMA circuit. Unused bits in the 8-bit data memory formats are filled with 0s. The BIAD register field is used to specify the starting address for the on-chip memory involved with the transfer. The 14-bit BEAD register specifies the starting address for the external byte memory space. The 8-bit BMPAGE register specifies the start- ing page for the external byte memory space. The BDIR register field selects the direction of the transfer. Finally, the 14-bit BWCOUNT register specifies the number of DSP words to transfer and initiates the BDMA circuit transfers. BDMA accesses can cross page boundaries during sequential addressing. A BDMA interrupt is generated on the completion of the number of transfers specified by the BWCOUNT register. The BWCOUNT register is updated after each transfer so it can be used to check the status of the transfers. When it reaches zero, the transfers have finished and a BDMA interrupt is gener- ated. The BMPAGE and BEAD registers must not be accessed by the DSP during BDMA operations. The source or destination of a BDMA transfer is always on-chip program or data memory. When the BWCOUNT register is written with a nonzero value the BDMA circuit starts executing byte memory accesses with wait states set by BMWAIT. These accesses continue until the count reaches zero. When enough accesses have occurred to Figure 9. Programmable Flag and Composite Control Register Figure 10. System Control Register BMWAIT CMSSEL 0 = DISABLE CMS 1 = ENABLE CMS DM(0x3FE6) PFTYPE 0=INPUT 1=OUTPUT (WHERE BIT: 11-IOM, 10-BM, 9-DM, 8-PM) 0 1 11 10 1 1 00 0 00 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4321 0 PROGRAMMABLE FLAG AND COMPOSITE SELECT CONTROL RESERVED RESERVED,ALW AYS SE T TO 0 SP O RT0 ENABL E 0= DIS ABL E 1 = E NABL E DM (0x3F FF) S YSTEM CONTROL S P ORT 1 E NABLE 0 = DISABLE 1 = E NABLE S PO RT1 C ONF IGURE 0= FI,FO , IRQ0, IRQ1, S CLK 1= SP O RT1 DIS ABLE BMS 0 = E NABL E BMS 1= DIS AB LEBMS PW AIT P RO GRAM M E MOR Y W AIT ST ATES 0 0 00 01 0 0 0 0 0 00 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 N OTE: RESERVED BITS ARE SHO WN O N A GRAY FIELD . THESE B ITS SHOUL D ALW AYS BE WR ITTEN W ITH Z EROS. R ESERVED SE T T O 0 Figure 11. BDMA Control Register Table 7. Data Formats BTYPE Internal Memory Space Word Size Alignment 00 Program memory 24 Full word 01 Data memory 16 Full word 10 Data memory 8 MSBs 11 Data memory 8 LSBs BDMA CONTROL BMPAGE BTYPE BDIR 0= LOAD FROM BM 1= STORE TO BM BCR 0 = RUN DURING BDMA 1 = HALT DURING BDMA 0 0 0 0 0 0 00 000 0 100 0 15 14 13 12 11 10 98 765 4 3 21 0 DM (0x3FE3) BDMA OVERLAY BITS (SEE TABLE 12) |
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