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EDJ2108EEBG Datasheet(PDF) 11 Page - Elpida Memory |
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EDJ2108EEBG Datasheet(HTML) 11 Page - Elpida Memory |
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11 / 32 page  EDJ2108EEBG, EDJ2116EEBG Data Sheet E1750E31 (Ver. 3.1) 11 1.4.2 Basic IDD and IDDQ Measurement Conditions Table 6: Basic IDD and IDDQ Measurement Conditions Parameter Symbol Description Operating one bank active precharge current IDD0 CKE: H; External clock: on; tCK, nRC, nRAS, CL: see Table 5; BL: 8*1; AL: 0; /CS: H between ACT and PRE; Command, address, bank address inputs: partially toggling according to Table 7; Data I/O: MID-LEVEL; DM: stable at 0; Bank activity: cycling with one bank active at a time: 0,0,1,1,2,2,... (see Table 7); Output buffer and RTT: enabled in MR*2; ODT signal: stable at 0; Pattern details: see Table 7 Operating one bank active-read-precharge current IDD1 CKE: H; External clock: On; tCK, nRC, nRAS, nRCD, CL: see Table 5; BL: 8*1, *6; AL: 0; /CS: H between ACT, RD and PRE; Command, address, bank address inputs, data I/O: partially toggling according to Table 8; DM: stable at 0; Bank activity: cycling with one bank active at a time: 0,0,1,1,2,2,... (see Table 8); Output buffer and RTT: enabled in MR*2; ODT Signal: stable at 0; Pattern details: see Table 8 Precharge standby current IDD2N CKE: H; External clock: on; tCK, CL: see Table 5 BL: 8*1; AL: 0; /CS: stable at 1; Command, address, bank address Inputs: partially toggling according to Table 9; data I/O: MID-LEVEL; DM: stable at 0; bank activity: all banks closed; output buffer and RTT: enabled in mode registers*2; ODT signal: stable at 0; pattern details: see Table 9 Precharge standby ODT current IDD2NT CKE: H; External clock: on; tCK, CL: see Table 5; BL: 8*1; AL: 0; /CS: stable at 1; Command, address, bank address Inputs: partially toggling according to Table 10; data I/O: MID-LEVEL; DM: stable at 0; bank activity: all banks closed; output buffer and RTT: enabled in MR*2; ODT signal: toggling according to Table 10; pattern details: see Table 10 Precharge standby ODT IDDQ current IDDQ2NT Same definition like for IDD2NT, however measuring IDDQ current instead of IDD current Precharge power-down current slow exit IDD2P0 CKE: L; External clock: on; tCK, CL: see Table 5; BL: 8*1; AL: 0; /CS: stable at 1; Command, address, bank address inputs: stable at 0; data I/O: MID-LEVEL; DM: stable at 0; bank activity: all banks closed; output buffer and RTT: EMR*2; ODT signal: stable at 0; precharge power down mode: slow exit*3 Precharge power-down current fast exit IDD2P1 CKE: L; External clock: on; tCK, CL: see Table 6; BL: 8*1; AL: 0; /CS: stable at 1; Command, address, bank address Inputs: stable at 0; data I/O: MID-LEVEL; DM:stable at 0; bank activity: all banks closed; output buffer and RTT: enabled in MR*2; ODT signal: stable at 0; precharge power down mode: fast exit*3 Precharge quiet standby current IDD2Q CKE: H; External clock: On; tCK, CL: see Table 5; BL: 8*1; AL: 0; /CS: stable at 1; Command, address, bank address Inputs: stable at 0; data I/O: MID-LEVEL; DM: stable at 0;bank activity: all banks closed; output buffer and RTT: enabled in MR*2; ODT signal: stable at 0 Active standby current IDD3N CKE: H; External clock: on; tCK, CL: see Table 5; BL: 8*1; AL: 0; /CS: stable at 1; Command, address, bank address Inputs: partially toggling according to Table 9; data I/O: MID-LEVEL; DM: stable at 0; bank activity: all banks open; output buffer and RTT: enabled in MR*2; ODT signal: stable at 0; pattern details: see Table 9 Active power-down current IDD3P CKE: L; External clock: on; tCK, CL: see Table 5; BL: 8*1; AL: 0; /CS: stable at 1; Command, address, bank address inputs: stable at 0; data I/O: MID-LEVEL; DM:stable at 0; bank activity: all banks open; output buffer and RTT: enabled in MR*2; ODT signal: stable at 0 Operating burst read current IDD4R CKE: H; External clock: on; tCK, CL: see Table 5; BL: 8*1, *6; AL: 0; /CS: H between RD; Command, address, bank address Inputs: partially toggling according to Table 11; data I/O: seamless read data burst with different data between one burst and the next one according to Table 11; DM: stable at 0; bank activity: all banks open, RD commands cycling through banks: 0,0,1,1,2,2,... (see Table 11); Output buffer and RTT: enabled in MR*2; ODT signal: stable at 0; pattern details: see Table 11 Operating burst read IDDQ current IDDQ4R Same definition like for IDD4R, however measuring IDDQ current instead of IDD current |
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