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EDJ4208EFBG-GN-F Datasheet(PDF) 4 Page - Elpida Memory |
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EDJ4208EFBG-GN-F Datasheet(HTML) 4 Page - Elpida Memory |
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4 / 29 page  EDJ4204EFBG, EDJ4208EFBG, EDJ4216EFBG Data Sheet E1922E20 (Ver. 2.0) 4 Pin Configurations ( × 16 configuration) /xxx indicates active low signal. Notes: 1. Not internally connected with die. 2. Input only pins (address, command, CKE, ODT and /RESET) do not supply termination. Pin name Function Pin name Function A0 to A14* 2 Address inputs A10(AP): Auto precharge A12(/BC): Burst chop /RESET* 2 Active low asynchronous reset BA0 to BA2* 2 Bank select VDD Supply voltage for internal circuit DQU0 to DQU7 DQL0 to DQL7 Data input/output VSS Ground for internal circuit DQSU, /DQSU DQSL, /DQSL Differential data strobe VDDQ Supply voltage for DQ circuit /CS* 2 Chip select VSSQ Ground for DQ circuit /RAS, /CAS, /WE* 2 Command input VREFDQ Reference voltage for DQ CKE* 2 Clock enable VREFCA Reference voltage for CA CK, /CK Differential clock input ZQ Reference pin for ZQ calibration DMU, DML Write data mask NC* 1 No connection ODT* 2 ODT control A B C D E F G H J K L VDDQ 1 VDDQ VSS NC 2 VDD VSS VSSQ DQU3 VDDQ VSSQ VSSQ VSS 3 DQU7 DQU5 DQU1 DMU DQL0 VDD /CAS /RAS 7 DQU4 /DQSU DQSU DQU0 DML /CK 8 VDDQ DQU6 VSSQ DQU2 VSSQ VDD VSSQ VDD M N P T VSS /RESET A13 A14 NC A8 9 VSS VDDQ VDDQ DQL2 DQL6 VSSQ VDDQ VREFDQ DQSL /DQSL DQL4 DQL1 VDD DQL3 VSS VSSQ DQL7 DQL5 VDDQ VSSQ VDDQ CK VSS NC VDD BA0 A3 A5 BA2 A0 A2 A12(/BC) A1 VREFCA BA1 A4 VSS VSS (Top view) 96-ball FBGA /CS /WE ODT VSS VSS R A7 A9 A11 A6 VDD VDD A10(AP) VSS VDD NC ZQ NC CKE |
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