 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
P82B96TD Datasheet(PDF) 11 Page - NXP Semiconductors |
|
||||||||||||||||||||||||||||||
P82B96TD Datasheet(HTML) 11 Page - NXP Semiconductors |
|
|
11 / 32 page  P82B96_8 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 08 — 10 November 2009 11 of 32 NXP Semiconductors P82B96 Dual bidirectional bus buffer Figure 13 shows how a master I2C-bus can be protected against short circuits or failures in applications that involve plug and socket connections and long cables that may become damaged. A simple circuit is added to monitor the SDA bus, and if its LOW time exceeds the design value, then the master bus is disconnected. P82B96 will free all its I/Os if its supply is removed, so one option is to connect its VCC to the output of a logic gate from, say, the 74LVC family. The SDA and SCL lines could be timed and VCC disabled via the gate if one or other lines exceeds a design value of ‘LOW’ period as in Figure 28 of AN255. If the supply voltage of logic gates restricts the choice of VCC supply then the low-cost discrete circuit in Figure 13 can be used. If the SDA line is held LOW, the 100 nF capacitor will charge and the Ry input will be pulled towards VCC. When it exceeds 0.5VCC the Ry input will set the Sy input HIGH, which in practice means simply releasing it. In this example the SCL line is made unidirectional by tying the Rx pin to VCC. The state of the buffered SCL line cannot affect the master clock line which is allowed when clock-stretching is not required. It is simple to add an additional transistor or diode to control the Rx input in the same way as Ry when necessary. The +V cable drive can be any voltage up to 15 V and the bus may be run at a lower impedance by selecting pull-up resistors for a static sink current up to 30 mA. VCC1 and VCC2 may be chosen to suit the connected devices. Because DDC uses relatively low speeds (< 100 kHz), the cable length is not restricted to 20 m by the I2C-bus signalling, but it may be limited by the video signalling. Fig 13. Extending a DDC bus P82B96 SCL Rx Tx 002aab989 Sx VCC Ry Ty Sy I2C-bus/DDC master SDA VCC1 GND Rx Tx Ry Ty VCC Sx Sy SCL SDA VCC2 GND I2C-bus/DDC slave 4.7 k Ω BC 847B 100 nF 100 k Ω +V cable drive 470 k Ω 470 k Ω BC 847B 3 m to 20 m cables I2C-bus/DDC R G B video signals PC/TV receiver/decoder box P82B96 monitor/flat TV +V cable drive |
Similar Part No. - P82B96TD |
|
Similar Description - P82B96TD |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.NET |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
