ADS8361

6

SBAS230E

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PIN CONFIGURATION

Top View

SSOP

BGND

CH B1+

CH B1–

CH B0+

CH B0–

CH A1+

CH A1–

CH A0+

CH A0–

AGND

1

2

3

4

5

6

7

8

9

10

11

12

24

23

22

21

20

19

18

17

16

15

14

13

SERIAL DATA A

SERIAL DATA B

BUSY

CLOCK

CS

RD

CONVST

A0

M0

M1

ADS8361

Top View

QFN

SSOP QFN

PIN

PIN

NAME

DESCRIPTION

128

BGND

Digital I/O Ground. Connect directly to analog ground (pin 12).

2

1

CH B1+

Noninverting Input Channel B1

3

2

CH B1–

Inverting Input Channel B1

4

3

CH B0+

Noninverting Input Channel B0

5

4

CH B0–

Inverting Input Channel B0

6

5

CH A1+

Noninverting Input Channel A1

7

6

CH A1–

Inverting Input Channel A1

8

7

CH A0+

Noninverting Input Channel A0

9

8

CH A0–

Inverting Input Channel A0

10

9

Reference Input

11

10

2.5V Reference Output

12

12

AGND

Analog Ground. Connect directly to digital ground (pin 1).

13

13

14

16

M1

Selects between the Serial Outputs. When M1 is LOW, both Serial Output A and Serial Output B are selected for data transfer. When M1

is HIGH, Serial output A is configured for both Channel A data and Channel B data; Serial Output B goes into tri-state (i.e., high impedance).

15

17

M0

Selects between two-channel and four-channel operation. When M0 is LOW, two-channel operation is selected and operates in

conjunction with A0. When A0 is HIGH, Channel A1 and Channel B1 are being converted. When A0 is LOW, Channel A0 and Channel

B0 are being converted. When M0 is HIGH, four-channel operation is selected. In this mode, all four channels are converted in sequence

starting with Channels A0 and B0, followed by Channels A1 and B1.

16

18

A0

A0 operates in conjunction with M0. With M0 LOW and A0 HIGH, Channel A1 and Channel B1 are converted. With M0 LOW and A0 LOW,

Channel A0 and Channel B0 are converted.

17

19

CONVST Convert Start. When CONVST switches from LOW to HIGH, the device switches from the sample to hold mode, independent of the status

of the external clock.

18

20

RD

Synchronization Pulse for the Serial Output.

19

21

CS

Chip Select. When LOW, the Serial Output A and Serial Output B outputs are active; when HIGH, the serial outputs are tri-stated.

20

22

CLOCK

An external CMOS-compatible clock can be applied to the CLOCK input to synchronize the conversion process to an external source.

21

23

BUSY

BUSY goes HIGH during a conversion and returns LOW after the third LSB has been transmitted on either the Serial A or Serial B output

pin.

22

24

SERIAL

The Serial Output data word is comprised of channel information and 16 bits of data. In operation, data is valid on the falling edge of

DCLOCK for 20 edges after the rising edge of RD.

23

25

SERIAL

The Serial Output data word is comprised of channel information and 16 bits of data. In operation, data is valid on the falling edge of

DCLOCK for 20 edges after the rising edge of RD. When M1 is HIGH, both Channel A data and Channel B data are available.

24

27

Digital I/O Power Supply, 2.7V to 5.5V

PIN DESCRIPTIONS

DATA B

DATA A

CH B1+

CH B1−

CH B0+

CH B0−

CH A1+

CH A1−

CH A0+

CH A0−

SERIAL DATA B

BUSY

CLOCK

CS

RD

CONVST

A0

M0

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

NOTE: (1) The thermal pad is internally connected to the substrate.

This pad can be connected to the analog ground or left floating.

Keep the thermal pad separate from the digital ground, if possible.

(2) NC = Not Connected.