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TCA8424RHAR Datasheet(PDF) 5 Page - Texas Instruments |
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TCA8424RHAR Datasheet(HTML) 5 Page - Texas Instruments |
5 / 30 page NACK ACK 9 8 2 1 Data Output by Receiver Data Output by Transmitter SCL From Master Start Condition S Clock Pulse for Acknowledgment SDA SCL Data Line Change SDA SCL S P Start Condition Stop Condition TCA8424 www.ti.com SCDS341 – MARCH 2013 A master receiver signals an end of data to the slave transmitter by not generating an acknowledge (NACK) after the last byte has been clocked out of the slave. This is done by the master receiver by holding the SDA line high. In this event, the transmitter must release the data line to enable the master to generate a Stop condition. NOTE Any communication to another device on the same I2C BUS must be terminated by a stop condition before communicating to the TCA8424. Any glitches below 0.7 × VCC on the SCL or SDA line should be less than 50 ns as per the I2C specification. Figure 1. Definition of Start and Stop Conditions Figure 2. Bit Transfer Figure 3. Acknowledgment on I2C Bus DEVICE I 2C ADDRESS The address of the device is shown below: Table 1. Address Reference SLAVE ADDRESS I2C BUS SLAVE ADDRESS B7 B6 B5 B4 B3 B2 B1 B0 0 1 1 1 0 1 1 0 (W) 134 (decimal), 76(h) 0 1 1 1 0 1 1 1 (R) 135 (decimal), 77(h) Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: TCA8424 |
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