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W949D6CBGX7G Datasheet(PDF) 4 Page - Winbond |
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W949D6CBGX7G Datasheet(HTML) 4 Page - Winbond |
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4 / 65 page  W989D6CB / W989D2CB 512Mb Mobile LPSDR Publication Release Date : August 07, 2013 - 4 - Revision : A01-006 9.3.5 WRITE with auto precharge interrupted by a WRITE (with or without auto precharge) .......................... 25 9.4 Burst Termination..............................................................................................................................25 9.5 Mode Register Operation ..................................................................................................................26 9.5.1 Burst Length field (A2~A0) ....................................................................................................................... 26 9.5.2 Addressing Mode Select (A3) .................................................................................................................. 26 9.5.3 Addressing Sequence for Sequential Mode............................................................................................. 27 9.5.4 Addressing Sequence for Interleave Mode.............................................................................................. 27 9.5.5 Addressing Sequence Example (Burst Length = 8 and Input Address is 13).......................................... 28 9.5.6 Read Cycle CAS Latency = 3................................................................................................................ 28 9.5.7 CAS Latency field (A6~A4).................................................................................................................... 29 9.5.8 Mode Register Definition .......................................................................................................................... 29 9.6 Extended Mode Register Description................................................................................................30 9.7 Simplified State Diagram...................................................................................................................31 10. CONTROL TIMING WAVEFORMS ......................................................................................... 32 10.1 Command Input Timing...................................................................................................................32 10.2 Read Timing....................................................................................................................................33 10.3 Control Timing of Input Data (x16) ..................................................................................................34 10.4 Control Timing of Output Data (x16) ...............................................................................................35 10.5 Control Timing of Input Data (x32) ..................................................................................................36 10.6 Control Timing of Output Data (x32) ...............................................................................................37 10.7 Mode register Set (MRS) Cycle ......................................................................................................38 10.8 Extended Mode register Set (EMRS) Cycle....................................................................................39 11. OPERATING TIMING EXAMPLE ............................................................................................ 40 11.1 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3).......................................................40 11.2 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Auto Precharge)............................41 11.3 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3).......................................................42 11.4 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Auto Precharge)............................43 11.5 Interleaved Bank Write (Burst Length = 8) ......................................................................................44 11.6 Interleaved Bank Write (Burst Length = 8, Auto Precharge) ...........................................................45 11.7 Page Mode Read (Burst Length = 4, CAS Latency = 3) ...............................................................46 11.8 Page Mode Read / Write (Burst Length = 8, CAS Latency = 3) ....................................................47 11.9 Auto Precharge Read (Burst Length = 4, CAS Latency = 3).........................................................48 11.10 Auto Precharge Write (Burst Length = 4) ......................................................................................49 11.11 Auto Refresh Cycle .......................................................................................................................50 11.12 Self Refresh Cycle ........................................................................................................................51 11.13 Power Down Mode........................................................................................................................52 11.14 Burst Read and Single Write (Burst Length = 4, CAS Latency = 3) ............................................53 11.15 Deep Power Down Mode Entry.....................................................................................................54 11.16 Deep Power Down Mode Exit .......................................................................................................55 11.17 Auto Precharge Timing (Read Cycle) ...........................................................................................56 11.18 Auto Precharge Timing (Write Cycle)............................................................................................57 11.19 Timing Chart of Read to Write Cycle.............................................................................................58 11.20 Timing Chart for Write to Read Cycle ...........................................................................................58 11.21 Timing Chart for Burst Stop Cycle (Burst Stop Command)...........................................................59 11.22 Timing Chart for Burst Stop Cycle (Precharge Command) ...........................................................59 11.23 CKE/DQM Input Timing (Write Cycle)...........................................................................................60 11.24 CKE/DQM Input Timing (Read Cycle)...........................................................................................61 12. PACKAGE DIMENSION.......................................................................................................... 62 12.1 : LPSDR X 16..................................................................................................................................62 12.2 : LPSDR X 32..................................................................................................................................63 13. REVISION HISTORY ............................................................................................................... 64 |
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