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NB3N51034 Datasheet(PDF) 5 Page - ON Semiconductor |
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NB3N51034 Datasheet(HTML) 5 Page - ON Semiconductor |
5 / 9 page NB3N51034 http://onsemi.com 5 Table 7. AC ELECTRICAL CHARACTERISTICS − PCI EXPRESS JITTER SPECIFICATIONS, VDD = 3.3 V ± 5%, TA = −40°C to 85°C Symbol Parameter Test Conditions Min Typ Max PCIe Industry Spec Unit tj (PCIe Gen 1) Phase Jitter Peak−to−Peak (Notes 16 and 19) f = 100 MHz, 25 MHz Crystal Input Evaluation Band: 0 Hz − Nyquist (clock frequency/2) SSOFF 10 20 86 ps SSON (−0.5%) 19 28 tREFCLK_HF_RMS (PCIe Gen 2) Phase Jitter RMS (Notes 17 and 19) f = 100 MHz, 25 MHz Crystal Input High Band: 1.5 MHz − Nyquist (clock frequency/2) SSOFF 1.0 1.8 3.1 ps SSON (−0.5%) 1.1 1.9 tREFCLK_LF_RMS (PCIe Gen 2) Phase Jitter RMS (Notes 17 and 19) f = 100 MHz, 25 MHz Crystal Input Low Band: 10 kHz − 1.5 MHz SSOFF 0.1 0.15 3.0 ps SSON (−0.5%) 0.8 1.1 tREFCLK_RMS (PCIe Gen 3) Phase Jitter RMS (Notes 18 and 19) f = 100 MHz, 25 MHz Crystal Input Evaluation Band: 0 Hz − Nyquist (clock frequency/2) SSOFF 0.35 0.7 1.0 ps SSON (−0.5%) 0.55 0.8 15.Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. 16.Peak−to−Peak jitter after applying system transfer function for the Common Clock Architecture. Maximum limit for PCI Express Gen 1 is 86 ps peak−to−peak for a sample size of 106 clock periods. 17.RMS jitter after applying the two evaluation bands to the two transfer functions defined in the Common Clock Architecture and reporting the worst case results for each evaluation band. Maximum limit for PCI Express Generation 2 is 3.1 ps RMS for tREFCLK_HF_RMS (High Band) and 3.0ps RMS for tREFCLK_LF_RMS (Low Band). 18.RMS jitter after applying system transfer function for the common clock architecture. 19.Measurement taken from differential output on single−ended channel terminated with RS = 33.2 W, RL = 50 W, with test load capacitance of 2 pF and current biasing resistor set at 475 W. See Figure 5. This parameter is guaranteed by characterization. Not tested in production. |
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