NB3U23CSQTCG datasheet(3/6 Pages) ONSEMI

Part #	NB3U23CSQTCG

Description	1.2 V Dual Channel CMOS Buffer / Translator

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Manufacturer	ONSEMI [ON Semiconductor]

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NB3U23C

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Table 3. MAXIMUM RATINGS (Note 2)

Symbol

Parameter

Condition 1

Condition 2

Rating

Unit

VDD

Supply Voltage

3.6

V

Vin

Input Voltage

–0.5 ≤ VI ≤ 2.5

V

ID

Output Current

25

mA

TA

Operating Temperature Range, Industrial

−40 to +85

°C

Tstg

Storage Temperature Range

−65 to +150

°C

qJA

Thermal Resistance (Junction−to−Ambient)

0 lfpm

500 lfpm (Note 3)

SC70−6

UDFN−6

210

126

TBD

°C/W

qJC

Thermal Resistance (Junction−to−Case)

(Note 3)

SC70−6

UDFN−6

100

TBD

°C/W

Tsol

Wave Solder

260

°C

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

2. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and not valid simultaneously. If

stress limits are exceeded device functional operation is not implied, damage may occur and reliability may be affected.

3. JEDEC standard multilayer board − 2S2P (2 signal, 2 power).

Table 4. ELECTRICAL CHARACTERISTICS (VDD = 1.2 ±5% V, GND = 0 V, TA = −40°C to +85°C)

Symbol

Characteristic

Conditions

Min

Typ

Max

Unit

DIDD

Power Supply Current

(Single Channel Switching @ 52 MHz)

CL = 20 pF

CL = 5 pF

CL = 1 pF

2.5

1.5

1

mA

Power Supply Current

(Both Channels Switching @ 52 MHz)

CL = 20 pF

CL = 5 pF

CL = 1 pF

5

3

2

mA

Ioff

Standby Current

Vi = VIH Max or GND;

VDD = 1.2 V, No Output Load

10

mA

VIH

Input High Voltage

0.65 * VDD

1.98

V

VIL

Input Low Voltage

0

0.35 * VDD

V

VOH

Output High Voltage

CL = 20 pF

RL = 100 kW

0.75 * VDD

VDD

V

VOL

Output Low Voltage

CL = 20 pF

RL = 100 kW

0

0.25 * VDD

V

Cin

Input Capacitance

5

pF

Fclk

Operating Frequency Range

0

52

MHz

tPD

Propagation Delay

INx to OUTx

CL = 20 pF, RL = 100 kW

5

ns

Phase Noise Floor Density

(Notes 4 and 5)

CL = 20 pF

RL = 100 kW

−150

dBc/Hz

Additive RMS Phase Jitter

(Notes 5 and 6)

CL = 20 pF

RL = 100 kW

Offset Frequency Range:

50 kHz to 10 MHz

0.15

0.25

ps

DC

Output Duty Cycle (Note 7)

Input Duty Cycle = 50%,

Min Input Slew Rate = 1 V/ns

45

55

%

tr/tf

Output Rise/Fall Times

0.2 * VDD to 0.8 * VDD

CL = 20 pF

RL = 100 kW

2

ns

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

4. White noise floor.

5. This parameter refers to the random jitter only.

6. The output RMS phase jitter can be calculated using the following equation:

(Output RMS Phase Jitter)2 = (Input RMS Phase Jitter)2 + (Additive RMS Phase Jitter)2

7. Measured with input voltage swing from 0 V to 1.8 V.

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