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ADSP-2185NKSTZ-3202 Datasheet(PDF) 1 Page - Analog Devices |
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ADSP-2185NKSTZ-3202 Datasheet(HTML) 1 Page - Analog Devices |
1 / 48 page a ICE-Port is a trademark of Analog Devices, Inc. DSP Microcomputer ADSP-218xN Series Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106 U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 © 2006 Analog Devices, Inc. All rights reserved. PERFORMANCE FEATURES 12.5 ns Instruction cycle time @1.8 V (internal), 80 MIPS sus- tained performance Single-cycle instruction execution Single-cycle context switch 3-bus architecture allows dual operand fetches in every instruction cycle Multifunction instructions Power-down mode featuring low CMOS standby power dissi- pation with 200 CLKIN cycle recovery from power-down condition Low power dissipation in idle mode INTEGRATION FEATURES ADSP-2100 family code compatible (easy to use algebraic syntax), with instruction set extensions Up to 256K byte of on-chip RAM, configured Up to 48K words program memory RAM Up to 56K words data memory RAM Dual-purpose program memory for both instruction and data storage Independent ALU, multiplier/accumulator, and barrel shifter computational units Two independent data address generators Powerful program sequencer provides zero overhead loop- ing conditional instruction execution Programmable 16-bit interval timer with prescaler 100-lead LQFP and 144-ball BGA SYSTEM INTERFACE FEATURES Flexible I/O allows 1.8 V, 2.5 V or 3.3 V operation All inputs tolerate up to 3.6 V regardless of mode 16-bit internal DMA port for high-speed access to on-chip memory (mode selectable) 4M-byte memory interface for storage of data tables and pro- gram overlays (mode selectable) 8-bit DMA to byte memory for transparent program and data memory transfers (mode selectable) Programmable memory strobe and separate I/O memory space permits “glueless” system design Programmable wait state generation Two double-buffered serial ports with companding hardware and automatic data buffering Automatic booting of on-chip program memory from byte- wide external memory, for example, EPROM, or through internal DMA Port Six external interrupts 13 programmable flag pins provide flexible system signaling UART emulation through software SPORT reconfiguration ICE-Port™ emulator interface supports debugging in final systems Figure 1. Functional Block Diagram A R ITH M E TIC UN ITS SH IFTE R MAC ALU P R O GRAM M EM O RY ADDR ES S DATA M EM O RY ADD RES S PR O GRAM M EMO R Y DATA DA TA ME MOR Y DA TA PO W E R-DO WN CONTRO L MEM OR Y PRO GRA M ME M ORY UP T O 48K 24-B IT EX TE RNAL ADDRES S BUS EX TE RNAL DATA BUS BY TE DM A CONT ROLL ER SP OR T0 S ERIAL PO RTS SP OR T 1 PROG RA MM ABL E I/O AND FLA GS TIM E R HOS T M ODE OR EX TE RNAL DATA BUS INTER NA L DM A PORT DAG1 DAT A ADDRES S G ENERAT OR S DAG2 PROG RAM SEQ U ENCER ADS P-2100 B AS E ARCHIT ECT UR E DATA ME M ORY UP T O 56K 16-B IT FU L L M EMOR Y MOD E |
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