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NB3V8312CMNG Datasheet(PDF) 3 Page - ON Semiconductor |
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NB3V8312CMNG Datasheet(HTML) 3 Page - ON Semiconductor |
3 / 11 page NB3V8312C http://onsemi.com 3 Figure 4. CLK_EN Control Timing Diagram CLK CLK_EN Q Table 2. OE, CLK_EN FUNCTION TABLES Inputs Outputs OE CLK_EN (Note 2) CLK Q[0:11] 0 X X Hi−Z 1 0 X Low 1 1 0 Low 1 1 1 High 2. The CLK_EN control input synchronously enables or disables the outputs as shown in Figure 4. This control latches on the falling edge of the selected input CLK. When CLK_EN is LOW, the outputs are disabled in a LOW state. When CLK_EN is HIGH, the outputs are enabled as shown. CLK_EN to CLK Set up and Hold times must be satisfied. |
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