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A29512-70 Datasheet(PDF) 3 Page - AMIC Technology |
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A29512-70 Datasheet(HTML) 3 Page - AMIC Technology |
3 / 31 page A29512 Series PRELIMINARY (November, 2001, Version 0.0) 2 AMIC Technology, Inc. The host system can detect whether a program or erase operation is complete by reading the I/O7 ( Data Polling) and I/O6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The A29512 is fully erased when shipped from the factory. The hardware sector protection feature disables operations for both program and erase in any combination of the Pin Configurations sectors of memory. This can be achieved via programming equipment. The Erase Suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any other sector that is not selected for erasure. True background erase can thus be achieved. Power consumption is greatly reduced when the device is placed in the standby mode. n DIP n PLCC NC NC A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 I/O3 VSS I/O4 I/O5 I/O6 I/O7 CE A10 OE A9 A8 A13 WE NC A14 VCC A11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 21 22 23 24 25 26 27 28 29 12 13 11 8 9 5 7 6 CE I/O7 A10 A29512L OE A11 A9 A8 A13 A14 10 n TSOP (Forward type) A29512V 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A9 A8 A13 A14 NC WE VCC NC A15 A12 A7 A6 A5 A4 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS I/O3 I/O4 I/O5 I/O6 I/O7 CE A10 OE A11 NC |
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