A65H73361 datasheet(10/21 Pages) AMICC

Part #	A65H73361

Description	128K x 36 & 256K x 18 Late Write Synchronous Fast SRAM with Pipelined Data Output

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Manufacturer	AMICC [AMIC Technology]

Direct Link	http://www.amictechnology.com

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A65H73361/A65H83181 Series

PRELIMINARY

(February, 1999, Version 2.0)

9

AMIC Technology, Inc.

AC Characteristics (TJ = 0 to +110

°C, VDD = 3.3V ± 5%)

Parameter

Symbol

-5

-6

-7

Units

Notes

Min.

Max.

Min.

Max.

Min.

Max.

Cycle Time

tKHKH

5

-

6.0

-

7.0

-

ns

Clock High Pulse Width

tKHKL

1.5

-

1.5

-

1.5

-

ns

Clock Low Pulse Width

tKLKH

1.5

-

1.5

-

1.5

-

ns

Clock to Output Valid

tKHQV

-

2.5

3.0

-

3.5

ns

1

Address Setup Time

tAVKH

0.5

-

0.5

-

0.5

-

ns

4

Address Hold Time

tKHAX

1.0

-

1.0

-

1.0

-

ns

4

Sync Select Setup Time

tSVKH

0.5

-

0.5

-

0.5

-

ns

4

Sync Select Hold Time

tKHSX

1.0

-

1.0

-

1.0

-

ns

4

Write Enables Setup Time

tWVKH

0.5

-

0.5

-

0.5

-

ns

4

Write Enables Hold Time

tKHWX

1.0

-

1.0

-

1.0

-

ns

4

Data In Setup Time

tDVKH

0.5

-

0.5

-

0.5

-

ns

4

Data In Hold Time

tKHDX

1.0

-

1.0

-

1.0

-

ns

4

Data Out Hold Time

tKHQX

0.5

-

0.5

-

0.5

-

ns

1

Clock High to Output High-z

tKHQZ

-

2.5

-

3.0

-

3.5

ns

1, 2

Clock high to Output Active

tXHQX4

1.0

-

1.0

-

1.0

-

ns

1, 2

Output Enable to High-z

tGHQZ

-

2.5

3.0

-

3.5

ns

1, 2

Output Enable to Low-z

tGLQX

0.5

-

0.5

-

0.5

-

ns

1, 2

Output Enable to Output Valid

tGLQV

-

2.5

-

3.0

-

3.5

ns

1

Output Enable Setup Time

tGHKH

0.5

-

0.5

-

0.5

-

ns

1, 3

Output Enable Hold Time

tKHGX

1.5

-

1.5

-

1.5

-

ns

1, 3

Sleep Mode Recovery Time

tZZR

5

-

6

-

7

-

ns

Sleep Mode Enable Time

tZZE

-

5

-

6

-

7

ns

1.See AC Test Loading figure on page 8.

2.Transitions are measured

± 200mV from steady state voltage.

3.Output Driver Impedance update specifications for G induced updates. Write and Deselect cycles will also induce

Output Driver Updates during High-z.

4.Inuse conditions VIH, VIL, Trise, Tfall of inputs must be withim 20% of VIH, VIL, Trise, Tfall of Clock.

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