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L7C109DMB25L Datasheet(PDF) 1 Page - LOGIC Devices Incorporated |
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L7C109DMB25L Datasheet(HTML) 1 Page - LOGIC Devices Incorporated |
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1 / 15 page  1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ1 DQ2 DQ3 VSS VCC A15 CE2 WE A13 A8 A9 A11 OE A10 CE DQ8 DQ7 DQ6 DQ5 DQ4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ1 DQ2 DQ3 VSS VCC A15 CE2 WE A13 A8 A9 A11 OE A10 CE DQ8 DQ7 DQ6 DQ5 DQ4 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 30 Top View 31 14 19 20 4 32 31 2 15 16 17 18 A7 A6 A5 A4 A3 A2 A1 A0 DQ1 WE A13 A8 A9 A11 OE A10 CE1 DQ8 LOGIC Devices Incorporated www.logicdevices.com 1 Feb 17, 2012 LDS-L7C108/9-G 1M Static RAMs 128K x 8 Static RAM L7C108 L7C109 128K x 8 Static RAM with Chip Select Powerdown, Output Enable and Single or Dual Chip Selects High Speed — to 15 ns maximum Operational Power, -L Version Active: 140 mA at 15 ns Standby: 1 mA max Data Retention at 2 V for Battery Backup Operation Screened to MIL-STD-883, Class B or to SMD 5962-89598 Package Styles Available: Pin Configuration FEATURES 32-pin Ceramic DIP 32-pin Ceramic SOJ 32-pin Quad CLCC 32-pin Ceramic LCC The L7C108 and L7C109 are high-perfor- mance, low-power CMOS static RAMs. The storage circuitry is organized as 131,072 words by 8 bits per word. The 8 Data In and Data Out signals share I/O pins. The L7C108 has a single active- low Chip Enable. The L7C109 has two devices are available in three speeds with maximum access times from 15 ns to 45 ns. Inputs and outputs are TTL compatible. Operation is from a single +5 V power supply. Power consumption is 140 mA retained in inactive storage with a supply voltage as low as 2 V. The L7C108 and L7C109 provide asyn- matching access and cycle times. The Chip Enables and a three-state I/O bus with a separate Output Enable control simplify the connection of several chips for increased storage capacity. Memory locations are specified on address pins A0 through A16. For the L7C108, reading from a designated location is accomplished by present- ing an address and driving CE1 and OE LOW while WE remains HIGH. For the L7C109, CE1 and OE must be LOW while CE2 and WE are HIGH.The data in the addressed memory location will then appear on the Data Out pins within one access time. The output pins stay in a high-impedance state when CE1 or OE is HIGH, or CE2 Writing to an addressed location is accomplished when the active-low CE1 and WE inputs are both LOW, and CE2 may be used to terminate the write oper- ation. Data In and Data Out signals have the same polarity. Latchup and static discharge protection are provided on-chip. The L7C108 and L7C109 can withstand an injection cur- rent of up to 200 mA on any pin without damage. OVERVIEW |
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