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LP62S1024BX-70LLT Datasheet(PDF) 7 Page - AMIC Technology |
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LP62S1024BX-70LLT Datasheet(HTML) 7 Page - AMIC Technology |
7 / 18 page LP62S1024B-T Series PRELIMINARY (October, 2002, Version 0.1) 6 AMIC Technology, Corp. AC Characteristics (TA = -25 °C to +85°C, VCC = 2.7V to 3.6V) Symbol Parameter LP62S1024B-55LLT LP62S1024B-70LLT Unit Min. Max. Min. Max. Read Cycle tRC Read Cycle Time 55 - 70 - ns tAA Address Access Time - 55 - 70 ns tACE1 Chip Enable Access Time CE1 - 55 - 70 ns tACE2 CE2 - 55 - 70 ns tOE Output Enable to Output Valid - 30 - 35 ns tCLZ1 Chip Enable to Output in Low Z CE1 10 - 10 - ns tCLZ2 CE2 10 - 10 - ns tOLZ Output Enable to Output in Low Z 5 - 5 - ns tCHZ1 Chip Disable to Output in High Z CE1 0 20 0 25 ns tCHZ2 CE2 0 20 0 25 ns tOHZ Output Disable to Output in High Z 0 20 0 25 ns tOH Output Hold from Address Change 5 - 10 - ns Write Cycle tWC Write Cycle Time 55 - 70 - ns tCW Chip Enable to End of Write 50 - 60 - ns tAS Address Setup Time 0 - 0 - ns tAW Address Valid to End of Write 50 - 60 - ns tWP Write Pulse Width 40 - 50 - ns tWR Write Recovery Time 0 - 0 - ns tWHZ Write to Output in High Z 0 25 0 25 ns tDW Data to Write Time Overlap 25 - 30 - ns tDH Data Hold from Write Time 0 - 0 - ns tOW Output Active from End of Write 5 - 5 - ns Notes: tCHZ1, tCHZ2, tOHZ, and tWHZ are defined as the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. |
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