LP62S16512U-70LLI datasheet(7/14 Pages) AMICC

Part #	LP62S16512U-70LLI

Description	512K X 16 BIT LOW VOLTAGE CMOS SRAM

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Manufacturer	AMICC [AMIC Technology]

Direct Link	http://www.amictechnology.com

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LP62S16512-I Series

PRELIMINARY

(March, 2002, Version 0.2)

7

AMIC Technology, Inc.

AC Characteristics (TA = -40

°C to +85°C, VCC = 2.7V to 3.6V)

Symbol

Parameter

LP62S16512-55LLI

LP62S16512-70LLI

Unit

Max.

Min.

Max.

Read Cycle

tRC

Read Cycle Time

55

-

70

-

ns

tAA

Address Access Time

-

55

-

70

ns

tAcs1 , tAcs2

Chip Enable Access Time

-

55

-

70

ns

tBE

Byte Enable Access Time

-

55

-

70

ns

tOE

Output Enable to Output Valid

-

25

-

35

ns

tCLZ1 , tCLZ2

Chip Enable to Output in Low Z

10

-

10

-

ns

tBLZ

Byte Enable to Output in Low Z

10

-

10

-

ns

tOLZ

Output Enable to Output in Low Z

5

-

5

-

ns

tCHZ1 , tCHZ2

Chip Disable to Output in High Z

-

20

-

25

ns

tBHZ

Byte Disable to Output in High Z

-

20

-

25

ns

tOHZ

Output Disable to Output in High Z

-

20

-

25

ns

tOH

Output Hold from Address Change

5

-

5

-

ns

Write Cycle

tWC

Write Cycle Time

55

-

70

-

ns

tCW1 , tCW2

Chip Enable to End of Write

50

-

60

-

ns

tBW

Byte Enable to End of Write

50

-

60

-

ns

tAS

Address Setup Time

0

-

0

-

ns

tAW

Address Valid to End of Write

50

-

60

-

ns

tWP

Write Pulse Width

40

-

50

-

ns

tWR

Write Recovery Time

0

-

0

-

ns

tWHZ

Write to Output in High Z

-

25

-

25

ns

tDW

Data to Write Time Overlap

25

-

30

-

ns

tDH

Data Hold from Write Time

0

-

0

-

ns

tOW

Output Active from End of Write

5

-

5

-

ns

Note: tCLZ1 , tCLZ2 , tBLZ , tOLZ , tCHZ1, tCHZ2 , tBHZ and tOHZ and tWHZ are defined as the time at which the outputs achieve the

open circuit condition and are not referred to output voltage levels.

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LP62S16512U-70LLI Datasheet(PDF) 7 Page - AMIC Technology

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