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PALCE20V8Q-15PI5 Datasheet(PDF) 5 Page - Advanced Micro Devices |
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PALCE20V8Q-15PI5 Datasheet(HTML) 5 Page - Advanced Micro Devices |
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5 / 16 page  AMD 2-159 PALCE20V8 Family Configuration Options Each macrocell can be configured as one of the follow- ing: registered output, combinatorial output, combinato- rial I/O or dedicated input. In the registered output configuration, the output buffer is enabled by the OE pin. In the combinatorial configuration, the buffer is either controlled by a product term or always enabled. In the dedicated input configuration, the buffer is always dis- abled. A macrocell configured as a dedicated input de- rives the input signal from an adjacent I/O. The macrocell configurations are controlled by the con- figuration control word. It contains 2 global bits (SG0 and SG1) and 16 local bits (SL00 through SL07 and SL10 through SL17). SG0 determines whether registers will be allowed. SG1 determines whether the PALCE20V8 will emulate a PAL20R8 family or a combinatorial de- vice. Within each macrocell, SL0x, in conjunction with SG1, selects the configuration of the macrocell and SL1x sets the output as either active low or active high. The configuration bits work by acting as control inputs for the multiplexers in the macrocell. There are four mul- tiplexers: a product term input, an enable select, an out- put select, and a feedback select multiplexer. SG1 and SL0x are the control signals for all four multiplexers. In MC0 and MC7, SG0 replaces SG1 on the feedback multiplexer. These configurations are summarized in table 1 and il- lustrated in figure 2. If the PALCE20V8 is configured as a combinatorial de- vice, the CLK and OE pins may be available as inputs to the array. If the device is configured with registers, the CLK and OE pins cannot be used as data inputs. Registered Output Configuration The control bit settings are SG0 = 0, SG1 = 1 and SL0x = 0. There is only one registered configuration. All eight product terms are available as inputs to the OR gate. Data polarity is determined by SL1x. SL1x is an input to the exclusive-OR gate which is the D input to the flip- flop. SL1x is programmed as 1 for inverted output or 0 for non-inverted output. The flip-flop is loaded on the LOW-to-HIGH transition of CLK. The feedback path is from Q on the register. The output buffer is enabled by OE. Combinatorial Configurations The PALCE20V8 has three combinatorial output con- figurations: dedicated output in a non-registered device, I/O in a non-registered device and I/O in a registered device. Dedicated Output in a Non-Registered Device The control settings are SG0 = 1, SG1 = 0, and SL0x = 0. All eight product terms are available to the OR gate. Al- though the macrocell is a dedicated output, the feed- back is used, with the exception of pins 18(21) and 19(23). Pins 18(21) and 19(23) do not use feedback in this mode. Dedicated Input in a Non-Registered Device The control bit settings are SG0 = 1, SG1 = 0 and SL0x = 1. The output buffer is disabled. The feedback signal is an adjacent I/O pin. Combinatorial I/O in a Non-Registered Device The control settings are SG0 = 1, SG1 = 1, and SL0x = 1. Only seven product terms are available to the OR gate. The eighth product term is used to enable the output buffer. The signal at the I/O pin is fed back to the AND array via the feedback multiplexer. This allows the pin to be used as an input. Combinatorial I/O in a Registered Device The control bit settings are SG0=0,SG1=1 and SL0x =1. Only seven product terms are available to the OR gate. The eighth product term is used as the output enable. The feedback signal is the corresponding I/O signal. Table 1. Macrocell Configurations SG0 SG1 SL0x Cell Configuration Devices Emulated Device has registers 0 1 0 Registered PAL20R8, 20R6, Output 20R4 0 1 1 Combinatorial I/O PAL20R6, 20R4 Device has no registers 1 0 0 Combinatorial PAL20L2, Output 18L4,16L6,14L8 1 0 1 Dedicated Input PAL20L2,18L4, 16L6 1 1 1 Combinatorial I/O PAL20L8 Programmable Output Polarity The polarity of each macrocell output can be active high or active low, either to match output signal needs or to reduce product terms. Programmable polarity allows Boolean expressions to be written in their most compact form (true or inverted), and the output can still be of the desired polarity. It can also save “DeMorganizing” efforts. Selection is made through a programmable bit SL1x which controls an exclusive-OR gate at the output of the AND/OR logic. The output is active high if SL1x is a 0 and active low if SL1x is a 1. |
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