LP62S4096EV-55LLI datasheet(10/14 Pages) AMICC

Part #	LP62S4096EV-55LLI

Description	512K X 8 BIT LOW VOLTAGE CMOS SRAM

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Manufacturer	AMICC [AMIC Technology]

Direct Link	http://www.amictechnology.com

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10 / 14 page

LP62S4096E-I Series

(January, 2002, Version 2.0)

10

AMIC Technology, Inc.

AC Test Conditions

Input Pulse Levels

0.4V to 2.4V

Input Rise and Fall Time

5 ns

Input and Output Timing Reference Levels

1.5V

Output Load

See Figures 1 and 2

30pF

* Including scope and jig.

CL

TTL

5pF

CL

TTL

Figure 1. Output Load

Figure 2. Output Load for tCLZ,

tOHZ, tOL, tCHZ, tWHZ, and tOW

Data Retention Characteristics (TA = -40

°C to 85°C)

Symbol

Parameter

Min.

Typ.

Max.

Unit

Conditions

VDR

VCC for Data Retention

2.0

-

3.6

V

CE1

≥ VCC - 0.2V, or

CE2

≤ 0.2V

VCC = 2.0V,

ICCDR

Data Retention Current

LL-Version

-

0.08

3*

µA

CE1

≥ VCC - 0.2V, or

CE2

≤ 0.2V

VIN

≤ 0V

tCDR

Chip Disable to Data Retention Time

0

-

ns

tR

Operation Recovery Time

tRC

-

ns

See Retention Waveform

tVR

VCC Rising Time from Data Retention Voltage to

Operating Voltage

5

-

ms

*

LP62S4096E-55LLI / 70LLI

ICCDR: max.

1

µA at TA = 0°C to + 40°C

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