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TLC32046MJ Datasheet(PDF) 10 Page - Texas Instruments |
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TLC32046MJ Datasheet(HTML) 10 Page - Texas Instruments |
10 / 56 page 1–4 FRAME SYNCHRONIZATION FUNCTIONS Function Frame Sync Output Receiving serial data on DX from processor to internal DAC FSX low Transmitting serial data on DR from internal ADC to processor, primary communications FSR low Transmitting serial data on DR from Data-DR to processor, secondary communications in dual-word (telephone interface) mode only FSD low TLC32046 Logic Levels TTL or CMOS TMS32020, TMS320C25, TMS320C30, or Equivalent 16-Bit DSP – 5 V 5 V FSD D11OUT Serial Data Out DR Serial Data In DX DATA-DR or CMOS Logic Levels 16-Bit Format TTL Secondary Communication (see Table above) Serial Data Input Analog Out Analog In OUT – OUT + IN – IN + FSR D10OUT FSX VCC – VCC + 20 19 26 25 22 21 1 5 4 3 12 14 11 13 Figure 1–1. Dual-Word (Telephone Interface) Mode When the DATA-DR/CONTROL input is tied to a logic signal source varying between 0 and 5 V, the TLC32046 is in the dual-word (telephone interface) mode. This logic signal is routed to the DR line for input to the DSP only when data frame synchronization (FSD) outputs a low level. The FSD pulse duration is 16 shift clock pulses. Also, in this mode, the control register data bits D10 and D11 appear on D10OUT and D11OUT, respectively, as outputs. |
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