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TMS320C6745CPTPA3 Datasheet(PDF) 9 Page - Texas Instruments |
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TMS320C6745CPTPA3 Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 227 page  TMS320C6745, TMS320C6747 www.ti.com SPRS377E – SEPTEMBER 2008 – REVISED FEBRUARY 2013 2 Device Overview 2.1 Device Characteristics Table 2-1 provides an overview of the C6745/6747 low power digital signal processor. The table shows significant features of the device, including the capacity of on-chip RAM, peripherals, and the package type with pin count. Table 2-1. Characteristics of the C6745/C6747 Processor HARDWARE FEATURES C6745 C6747 EMIFB 16bit, up to 128MB SDRAM 16/32bit, up to 256MB SDRAM Asynchronous (8/16-bit bus width) RAM, Asynchronous (8-bit bus width) RAM, EMIFA Flash, 16bit up to 128MB SDRAM, NOR, Flash, NOR, NAND NAND Flash Card Interface MMC and SD cards supported. EDMA3 32 independent channels, 8 QDMA channels, 2 Transfer controllers 2 64-Bit General Purpose (each configurable as 2 separate 32-bit timers, 1 configurable Timers as Watch Dog) UART 3 (one with RTS and CTS flow control) SPI 2 (each with one hardware chip select) I2C 2 (both Master/Slave) Multichannel Audio 2 (each with transmit/receive, FIFO buffer, 3 (each with transmit/receive, FIFO buffer, Serial Port [McASP] 16/9 serializers) 16/9 serializers) Peripherals 10/100 Ethernet MAC with Management Data 1 (RMII Interface) Not all peripherals pins I/O are available at the eHRPWM 6 Single Edge, 6 Dual Edge Symmetric, or 3 Dual Edge Asymmetric Outputs same time (for more detail, see the Device eCAP 3 32-bit capture inputs or 3 32-bit auxiliary PWM outputs Configurations section). eQEP 2 32-bit QEP channels with 4 inputs/channel UHPI - 1 (16-bit multiplexed address/data) Full Speed Host Or Device with On-Chip High-Speed OTG Controller with on-chip USB 2.0 (USB0) PHY OTG PHY Full-Speed OHCI (as host) with on-chip USB 1.1 (USB1) - PHY General-Purpose 8 banks of 16-bit Input/Output Port LCD Controller - 1 1 (32 KHz oscillator and seperate power RTC - trail. Provides time and date tracking and alarm capability.) PRU Subsystem 2 Programmable PRU Cores (PRUSS) Size (Bytes) 320 KB RAM 448 KB RAM DSP 32KB L1 Program (L1P)/Cache (up to 32KB) 32KB L1 Data (L1D)/Cache (up to 32KB) On-Chip Memory 256KB Unified Mapped RAM/Cache (L2) Organization DSP Memories can be made accessible to EDMA3, and other peripherals. ADDITIONAL MEMORY - 128KB RAM C674x CPU ID + CPU Control Status Register 0x1400 Rev ID (CSR.[31:16]) C674x Megamodule Revision ID Register 0x0000 Revision (MM_REVID[15:0]) 0x0B7D F02F (Silicon Revision 1.0) JTAG BSDL_ID DEVIDR0 register 0x8B7D F02F (Silicon Revision 1.1) 0x9B7D F02F (Silicon Revisions 3.0, 2.1, and 2.0) Copyright © 2008–2013, Texas Instruments Incorporated Device Overview 9 Submit Documentation Feedback Product Folder Links: TMS320C6745 TMS320C6747 |
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