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TMS320F240PQS Datasheet(PDF) 5 Page - Texas Instruments |
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TMS320F240PQS Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 105 page  TMS320F240 DSP CONTROLLER SPRS042E – OCTOBER 1996 – REVISED NOVEMBER 2002 5 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 Terminal Functions TERMINAL TYPE† DESCRIPTION NAME NO. TYPE† DESCRIPTION EXTERNAL INTERFACE DATA/ADDRESS SIGNALS A0 (LSB) A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 (MSB) 110 111 112 114 115 116 117 118 119 122 123 124 125 126 127 128 O/Z Parallel address bus A0 [least significant bit (LSB)] through A15 [most significant bit (MSB)]. A15–A0 are multiplexed to address external data/program memory or I/O. A15–A0 are placed in high-impedance state when EMU1/OFF is active low and hold their previous states in power-down modes. D0 (LSB) D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 (MSB) 9 10 11 12 15 16 17 18 19 22 23 24 25 26 27 28 I/O/Z Parallel data bus D0 (LSB) through D15 (MSB). D15–D0 are multiplexed to transfer data between the TMS320F240 and external data/program memory and I/O space (devices). D15–D0 are placed in the high-impedance state when not outputting, when in power-down mode, when reset (RS) is asserted, or when EMU1/OFF is active low. EXTERNAL INTERFACE CONTROL SIGNALS DS PS IS 129 131 130 O/Z Data, program, and I/O space select signals. DS, PS, and IS are always high unless low-level asserted for communication to a particular external space. They are placed in the high-impedance state during reset, power down, and when EMU1/OFF is active low. READY 36 I Data ready. READY indicates that an external device is prepared for the bus transaction to be completed. If the device is not ready (READY is low), the processor waits one cycle and checks READY again. R/W 4 O/Z Read/write signal. R/W indicates transfer direction during communication to an external device. It is normally in read mode (high), unless low level is asserted for performing a write operation. It is placed in the high-impedance state during reset, power down, and when EMU1/OFF is active low. STRB 6 O/Z Strobe. STRB is always high unless asserted low to indicate an external bus cycle. It is placed in the high-impedance state during reset, power down, and when EMU1/OFF is active low. WE 1 O/Z Write enable. The falling edge of WE indicates that the device is driving the external data bus (D15–D0). Data can be latched by an external device on the rising edge of WE. WE is active on all external program, data, and I/O writes. WE goes in the high-impedance state following reset and when EMU1/OFF is active low. W/R 132 O/Z Write/read. W/R is an inverted form of R/W and can connect directly to the output enable of external devices. W/R is placed in the high-impedance state following reset and when EMU1/OFF is active low. † I = input, O = output, Z = high impedance |
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