74AVC2T45GT datasheet(11/27 Pages) NXP

Part #	74AVC2T45GT

Description	Dual-bit, dual-supply voltage level translator/transceiver; 3-state

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74AVC2T45

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Product data sheet

Rev. 7 — 8 February 2013

11 of 27

NXP Semiconductors

74AVC2T45

Dual-bit, dual-supply voltage level translator/transceiver; 3-state

[1]

tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH.

ten is a calculated value using the formula shown in Section 13.4 “Enable times”

Table 13.

Dynamic characteristics for temperature range

40 C to +125 C [1]

Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8; for wave forms see Figure 6 and Figure 7

Symbol Parameter

Conditions

VCC(B)

Unit

1.2 V

 0.1 V

1.5 V

 0.1 V 1.8 V  0.15 V 2.5 V  0.2 V

3.3 V

 0.3 V

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

VCC(A) = 1.1 V to 1.3 V

tpd

propagation

delay

A to B

1.0

9.9

0.7

7.5

0.6

6.8

0.5

6.3

0.5

6.8

ns

B to A

1.0

9.9

0.8

8.8

0.7

8.5

0.6

8.0

0.5

7.9

ns

tdis

disable time

DIR to A

2.2

9.7

2.2

9.7

2.2

9.7

2.2

9.7

2.2

9.7

ns

DIR to B

2.2

9.2

1.8

7.4

2.0

7.6

1.7

6.9

2.4

8.0

ns

ten

enable time

DIR to A

-

19.1

-

16.2

-

16.1

-

14.9

-

15.9

ns

DIR to B

-

19.6

-

17.2

-

16.5

-

16.0

-

16.5

ns

VCC(A) = 1.4 V to 1.6 V

tpd

propagation

delay

A to B

1.0

8.8

0.7

6.0

0.6

5.1

0.5

4.1

0.5

3.9

ns

B to A

1.0

7.5

0.8

6.0

0.7

5.7

0.6

5.2

0.5

5.0

ns

tdis

disable time

DIR to A

1.6

7.0

1.6

7.0

1.6

7.0

1.6

7.0

1.6

7.0

ns

DIR to B

2.0

8.3

1.8

6.5

1.6

6.6

1.2

5.3

1.7

6.1

ns

ten

enable time

DIR to A

-

15.8

-

12.5

-

12.3

-

10.5

-

11.1

ns

DIR to B

-

15.8

-

13.0

-

12.1

-

11.1

-

10.9

ns

VCC(A) = 1.65 V to 1.95 V

tpd

propagation

delay

A to B

1.0

8.5

0.6

5.7

0.5

4.8

0.5

3.8

0.5

3.5

ns

B to A

1.0

6.8

0.7

5.1

0.5

4.9

0.5

4.3

0.5

4.1

ns

tdis

disable time

DIR to A

1.6

6.1

1.6

6.1

1.6

6.1

1.6

6.1

1.6

6.1

ns

DIR to B

1.8

8.5

1.8

6.3

1.4

6.4

1.0

5.0

1.5

5.8

ns

ten

enable time

DIR to A

-

15.3

-

11.4

-

11.3

-

9.3

-

9.9

ns

DIR to B

-

14.6

-

11.8

-

10.9

-

9.9

-

9.6

ns

VCC(A) = 2.3V to 2.7V

tpd

propagation

delay

A to B

1.0

8.0

0.5

5.2

0.5

4.3

0.5

3.3

0.5

2.9

ns

B to A

1.0

6.3

0.6

4.2

0.5

3.8

0.5

3.3

0.5

3.1

ns

tdis

disable time

DIR to A

1.5

4.7

1.5

4.7

1.5

4.7

1.5

4.7

1.5

4.7

ns

DIR to B

1.7

8.0

2.0

5.8

1.5

5.7

0.6

4.7

1.1

5.3

ns

ten

enable time

DIR to A

-

14.3

-

10.0

-

9.5

-

8.0

-

8.4

ns

DIR to B

-

12.7

-

9.9

-

9.0

-

8.0

-

7.6

ns

VCC(A) = 3.0V to 3.6V

tpd

propagation

delay

A to B

1.0

7.9

0.5

5.0

0.5

4.1

0.5

3.1

0.5

2.7

ns

B to A

1.0

6.8

0.6

4.0

0.5

3.5

0.5

2.9

0.5

2.7

ns

tdis

disable time

DIR to A

1.5

5.2

1.5

5.2

1.5

5.2

1.5

5.2

1.5

5.2

ns

DIR to B

1.7

7.9

0.7

6.1

0.6

6.1

0.7

4.6

1.7

5.2

ns

ten

enable time

DIR to A

-

14.7

-

10.1

-

9.6

-

7.5

-

7.9

ns

DIR to B

-

13.1

-

10.2

-

9.3

-

8.3

-

7.9

ns

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