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TPIC2603DWR Datasheet(PDF) 1 Page - Texas Instruments |
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TPIC2603DWR Datasheet(HTML) 1 Page - Texas Instruments |
1 / 19 page TPIC2603 6CHANNEL SERIAL INTERFACE LOW SIDE DRIVER SLIS056A − FEBRUARY 1995 − REVISED MARCH 1996 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 D Serial Control With Diagnostics D Six Power DMOS Transistor Outputs of 350-mA Continuous Current D Internal 60-V Inductive Load Clamp D Independent ON-State Shorted-Load/Short-to-Battery Fault Detection on All Drain Terminals D Independent OFF-State Open-Load Fault Sense on All Drain Terminals D Transition of Drain Outputs to Low Duty Cycle Pulsed-Width-Modulation (PWM) Mode for Over-Current Condition D Over-Battery-Voltage-Lockout Protection D Over-Temperature Sense With Serial Interface Fault Status D Fault Diagnostics Returned Through Serial Output Terminal D Internal Power-On Reset of Registers D CMOS Compatible Inputs With Hysteresis description The TPIC2603 is a monolithic low-side driver which provides serial interface and diagnostics to control six on-board power DMOS switches. Each channel has independent OFF-state open-load sense, ON-state shorted-load/short-to-battery protection, over-battery-voltage-lockout protection, and over-temperature sense with fault status reported through the serial interface. The device also provides inductive voltage transient protection for each drain output. The TPIC2603 drives inductive and resistive loads such as relays, valves, and lamps. Serial data input (SDI) is transferred through the serial register when CS is low on low-to-high transitions of the serial clock (SCLK). Each string of data must consist of 8 or 16 bits of data. A logic high input data bit turns the respective output channel ON and a logic low data bit turns it OFF. CS must be transited high after all of the serial data has been clocked into the device. A low-to-high transition of CS transfers the last six bits of serial data to the output buffer, places the serial data out (SDO) terminal in a high-impedance state, and re-enables the fault register. Fault data for the device is sent out the SDO terminal. The first bit of the shift register is exclusively ORed with the fault registers. When a fault exists, the SDI data is inverted as it is transferred out of SDO. Fault data consists of fault flags for over-temperature (bit 6) and shorted/open-load (bits 0-5) for each of the six output channels. Fault register bits are set or cleared asynchronously, when CS is high to reflect the current state of the hardware. The fault must be present when CS is transited from high to low to be captured and reported in the serial fault data. New faults cannot be captured in the serial register when CS is low. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1996, Texas Instruments Incorporated 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 DRAIN5 DRAIN4 SCLK SDI GND GND SDO CS DRAIN3 DRAIN2 Vbat DRAIN0 NC NC GND GND NC NC DRAIN1 VCC NE PACKAGE (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 DRAIN5 DRAIN4 SCLK SDI GND GND GND GND SDO CS DRAIN3 DRAIN2 Vbat DRAIN0 NC NC GND GND GND GND NC NC DRAIN1 VCC DW PACKAGE (TOP VIEW) NC − No internal connection PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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