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ACPL-K376-000E Datasheet(PDF) 7 Page - AVAGO TECHNOLOGIES LIMITED |
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ACPL-K376-000E Datasheet(HTML) 7 Page - AVAGO TECHNOLOGIES LIMITED |
7 / 13 page 7 Table 7. Switching Specifications Unless otherwise noted, TA = –40°C to +105°C. Parameter Sym Device Min Typ[1] Max Units Test Conditions/Notes Fig. VCC = 4.5 V Propagation Delay Time to Logic Low at Output tPHL ACPL-K370 3.7 7.5 PsRL = 4.7 k:, CL = 30 pF; Note 2 10 ACPL-K376 6.2 12.5 Ps ACPL-K370 3.7 7.5 PsRL = 1.8 k:, CL = 15 pF; Note 2 ACPL-K376 6.3 12.5 Ps Propagation Delay Time to Logic High at Output tPLH ACPL-K370 13.8 70 PsRL = 4.7 k:, CL = 30 pF; Note 3 10 ACPL-K376 13.3 70 Ps ACPL-K370 8.5 45 PsRL = 1.8 k:, CL = 15 pF; Note 3 ACPL-K376 6.4 45 Ps Output Rise Time (10-90%) tR ACPL-K370 25 PsRL = 4.7 k:, CL = 30 pF 11 ACPL-K376 24 Ps Output Fall Time (90-10%) tF ACPL-K370 0.3 PsRL = 4.7 k:, CL = 30 pF 11 ACPL-K376 0.4 Ps VCC = 3.3 V Propagation Delay Time to Logic Low at Output tPHL ACPL-K370 4 7.5 PsRL = 4.7 k:, CL = 30 pF; Note 2 ACPL-K376 6.8 12.5 Ps ACPL-K370 4 7.5 PsRL = 1.8 k:, CL = 15 pF; Note 2 ACPL-K376 6.9 12.5 Ps Propagation Delay Time to Logic High at Output tPLH ACPL-K370 19 90 PsRL = 4.7 k:, CL = 30 pF; Note 3 ACPL-K376 18.5 90 Ps ACPL-K370 12.8 70 PsRL = 1.8 k:, CL = 15 pF; Note 3 ACPL-K376 12.5 70 Ps Output Rise Time (10-90%) tR ACPL-K370 27 PsRL = 4.7 k:, CL = 30 pF ACPL-K376 26 Ps Output Fall Time (90-10%) tF ACPL-K370 0.3 PsRL = 4.7 k:, CL= 30 pF ACPL-K376 0.5 Ps VCC = 3 V to 5.5 V Common Mode Transient Immunity at Logic High Output |CMH| 10 kV/ PsIIN = 0 mA, RL = 4.7 k:, VO,MIN = 2 V, VCM = 1500 V; Notes 4, 5 Common Mode Transient Immunity at Logic Low Output |CML| ACPL-K370 1 kV/ PsIIN = 3.11 mA, RL = 4.7 k:, VO,MAX = 0.8 V, VCM = 500 V; Notes 4, 5 ACPL-K376 1 kV/ PsIIN = 1.56 mA, RL = 4.7 k:, VO,MAX = 0.8 V, VCM = 500 V; Notes 4, 5 Notes: 1. All typical values are at TA = 25°C unless otherwise stated. 2. The tPHL propagation delay is measured from the 2.5 V level of the leading edge of a 5.0 V input pulse (1 Ps rise time) to the 1.5 V level on the leading edge of the output pulse. CL includes probe and stray wiring capacitance. 3. The tPLH propagation delay is measured from the 2.5 V level of the trailing edge of a 5.0 V input pulse (1 Ps fall time) to the 1.5 V level on the trailing edge of the output pulse. CL includes probe and stray wiring capacitance. 4. Common mode transient immunity with a logic “High” level is the maximum tolerable (positive) dVCM/dt on the leading edge of the common mode pulse, VCM, to insure that the output will remain in a logic“High”state (i.e., VO > 2.0 V). Common mode transient immunity in logic“Low”level is the maximum tolerable (negative) dVCM/dt on the trailing edge of the common mode pulse signal, VCM, to insure that the output will remain in a logic “Low” state (i.e., VO < 0.8 V). 5. In applications where dVCM/dt may exceed 50 kV / μs (such as when a static discharge occurs), a series resistor, RCC, should be included to protect the detector IC from destructive high surge currents. The recommended value for RCC is 240 : per volt of allowable drop in VCC (between pin 8 and VCC) with a minimum value of 240 :. |
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