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ADSP-21363BBCZ-1AA Datasheet(PDF) 3 Page - Analog Devices |
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ADSP-21363BBCZ-1AA Datasheet(HTML) 3 Page - Analog Devices |
3 / 56 page ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Rev. G | Page 3 of 56 | March 2011 GENERAL DESCRIPTION The ADSP-2136x SHARC ® processor is a member of the SIMD SHARC family of DSPs that feature Analog Devices, Inc., Super Harvard Architecture. The processor is source code-compatible with the ADSP-2126x and ADSP-2116x DSPs, as well as with first generation ADSP-2106x SHARC processors in SISD (single-instruction, single-data) mode. The ADSP-2136x are 32-/40-bit floating-point processors optimized for high performance automotive audio applications. They contain a large on-chip SRAM and ROM, multiple internal buses to elim- inate I/O bottlenecks, and an innovative digital audio interface (DAI). As shown in the functional block diagram on Page 1, the ADSP-2136x uses two computational units to deliver a signifi- cant performance increase over the previous SHARC processors on a range of signal processing algorithms. With its SIMD com- putational hardware, the ADSP-2136x can perform two GFLOPS running at 333 MHz. Table 1 shows performance benchmarks for these devices. Table 2 shows the features of the individual product offerings. The diagram on Page 1 shows the two clock domains that make up the ADSP-2136x processors. The core clock domain contains the following features: • Two processing elements, each of which comprises an ALU, multiplier, shifter, and data register file • Data address generators (DAG1, DAG2) • Program sequencer with instruction cache • PM and DM buses capable of supporting four 32-bit data transfers between memory and the core at every core pro- cessor cycle • One periodic interval timer with pinout •On-chip SRAM (3M bit) • On-chip mask-programmable ROM (4M bit) • JTAG test access port for emulation and boundary scan. The JTAG provides software debug through user break- points, which allow flexible exception handling. The diagram on Page 1 also shows the following architectural features: • I/O processor that handles 32-bit DMA for the peripherals • Six full duplex serial ports • Two SPI-compatible interface ports—primary on dedi- cated pins, secondary on DAI pins • 8-bit or 16-bit parallel port that supports interfaces to off- chip memory peripherals • Digital audio interface that includes two precision clock generators (PCG), an input data port (IDP), an S/PDIF receiver/transmitter, 8-channel asynchronous sample rate converter, DTCP cipher, six serial ports, eight serial inter- faces, a 20-bit parallel input port, 10 interrupts, six flag outputs, six flag inputs, three timers, and a flexible signal routing unit (SRU) Table 1. Benchmarks (at 333 MHz) Benchmark Algorithm Speed (at 333 MHz) 1024 Point Complex FFT (Radix 4, with reversal) 27.9 μs FIR Filter (per tap)1 1 Assumes two files in multichannel SIMD mode. 1.5 ns IIR Filter (per biquad)1 6.0 ns Matrix Multiply (pipelined) [3×3] × [3×1] [4×4] × [4×1] 13.5 ns 23.9 ns Divide (y/x) 10.5 ns Inverse Square Root 16.3 ns Table 2. ADSP-2136x Family Features Feature ADSP-21362 ADSP-21363 ADSP-21364 ADSP-21365 ADSP-21366 RAM ROM 3M bit 4M bit 3M bit 4M bit 3M bit 4M bit 3M bit 4M bit 3M bit 4M bit Audio Decoders in ROM1 No No No Yes Yes Pulse-Width Modulation Yes Yes Yes Yes Yes S/PDIF Yes No Yes Yes Yes DTCP2 Yes No No Yes No SRC SNR Performance –128 dB No SRC –140 dB –128 dB –128 dB 1 Audio decoding algorithms include PCM, Dolby Digital EX, Dolby Pro Logic IIx, DTS 96/24, Neo:6, DTS ES, MPEG-2 AAC, MP3, and functions like bass management, delay, speaker equalization, graphic equalization, and more. Decoder/post-processor algorithm combination support varies depending upon the chip version and the system configurations. Please visit www.analog.com for complete information. 2 The ADSP-21362 and ADSP-21365 processors provide the Digital Transmission Content Protection protocol, a proprietary security protocol. Contact your Analog Devices sales office for more information. |
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