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PCF8583T Datasheet(PDF) 6 Page - NXP Semiconductors |
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PCF8583T Datasheet(HTML) 6 Page - NXP Semiconductors |
6 / 37 page PCF8583 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 — 6 October 2010 6 of 37 NXP Semiconductors PCF8583 Clock and calendar with 240 x 8-bit RAM 7.3 Control and status register The control and status register is defined as the memory location 00h with free access for reading and writing via the I2C-bus. All functions and options are controlled by the contents of the control and status register (see Figure 5). Fig 5. Control and status register timer flag: alarm flag: alarm enable bit: mask flag: function mode: 00 01 10 11 hold last count flag: logic 0: logic 1: stop counting flag: logic 0: logic 1: 7 6 5 4 321 0 MSB LSB 013aaa370 memory location 00h reset state: 0000 0000 alarm disabled: flags toggle alarm control register to disabled (memory locations 08h to 0Fh are free RAM space) logic 1: enable alarm control register (memory location 08h is the alarm control register) logic 0: read locations 05h to 06h unmasked logic 1: read date and month count directly 50 % duty factor seconds flag if alarm enable bit is logic 0 50 % duty factor minutes flag if alarm enable bit is logic 0 logic 0: clock mode 32.768 kHz clock mode 50 Hz event-counter mode test modes store and hold last count in capture latches count count pulses stop counting, reset divider |
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