DS90LV032A

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SNLS011C – JULY 1999 – REVISED APRIL 2013

DS90LV032A 3V LVDS Quad CMOS Differential Line Receiver

Check for Samples: DS90LV032A

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FEATURES

DESCRIPTION

The DS90LV032A is a quad CMOS differential line

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>400 Mbps (200 MHz) switching rates

receiver designed for applications requiring ultra low

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0.1 ns channel-to-channel skew (typical)

power dissipation and high data rates. The device is

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0.1 ns differential skew (typical)

designed to support data rates in excess of 400 Mbps

(200 MHz) utilizing Low Voltage Differential Signaling

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3.3 ns maximum propagation delay

(LVDS) technology.

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3.3V power supply design

The DS90LV032A accepts low voltage (350 mV

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Power down high impedance on LVDS inputs

typical) differential input signals and translates them

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Low Power design (40mW @ 3.3V static)

to 3V CMOS output levels. The receiver supports a

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Interoperable with existing 5V LVDS networks

outputs. The receiver also supports open, shorted

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Accepts small swing (350 mV typical) VID

and terminated (100

Ω) input Fail-safe. The receiver

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Supports open, short and terminated input fail-

output will be HIGH for all fail-safe conditions.

safe

The DS90LV032A and companion LVDS line driver

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Compatible with ANSI/TIA/EIA-644

(eg. DS90LV031A) provide a new alternative to high

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Industrial temp. operating range (-40°C to

power PECL/ECL devices for high speed point-to-

+85°C)

point interface applications.

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Available in SOIC and TSSOP Packaging

Connection Diagram

Order Number DS90LV032ATM

or DS90LV032ATMTC

D-16 and PW-16 Packages

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PRODUCTION DATA information is current as of publication date.

Copyright © 1999–2013, Texas Instruments Incorporated

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.