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MCF5275LCVM166 Datasheet(PDF) 9 Page - Freescale Semiconductor, Inc |
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MCF5275LCVM166 Datasheet(HTML) 9 Page - Freescale Semiconductor, Inc |
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9 / 44 page  Design Recommendations MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 4 Freescale Semiconductor 9 5 Design Recommendations 5.1 Layout • Use a 4-layer printed circuit board with the VDD and GND pins connected directly to the power and ground planes for the MCF5275. • See application note AN1259 System Design and Layout Techniques for Noise Reduction in MCU-Based Systems. • Match the PC layout trace width and routing to match trace length to operating frequency and board impedance. Add termination (series or therein) to the traces to dampen reflections. Increase the PCB impedance (if possible) keeping the trace lengths balanced and short. Then do cross-talk analysis to separate traces with significant parallelism or are otherwise "noisy". Use 6 mils trace and separation. Clocks get extra separation and more precise balancing. 5.2 Power Supply • 33uF, 0.1 μF, and 0.01 μF across each power supply VSSPLL — — — I K16 L13 VSS — — — I A1, A10, A16, E5, E12, F6, F11, G7:10, H7:10, J1, J7:10, K7:10, L6, L11, M5, N16, R7, T1, T16 F7, F8, G6:9, H6:9, J7, J8 OVDD — — — I E6:8, F5, F7, F8, G5, G6, H5, H6, J11, J12, K11, K12, L9, L10, L12, M9:11 E5:7, F5, F6, H10, J9, J10, K8:10 VDD — — — I D8, H13, K4, N8 D6, G5, G12, L7 SD_VDD — — — I E9:11, F9, F10, F12, G11, G12, H11, H12, J5, J6, K5, K6, L5, L7, L8, M6, M7, M8 E8:10, F9, F10, G10, H5, J5, J6, K5:7 1 Refers to pin’s primary function. All pins which are configurable for GPIO have a pullup enabled in GPIO mode with the exception of PBUSCTL[7], PBUSCTL[4:0], PADDR, PBS, PSDRAM. 2 If JTAG_EN is asserted, these pins default to Alternate 1 (JTAG) functionality. The GPIO module is not responsible for assigning these pins. Table 2. MCF5274 and MCF5275 Signal Information and Muxing (continued) Signal Name GPIO Alternate1 Alternate2 Dir.1 MCF5274 MCF5275 256 MAPBGA MCF5274L MCF5275L 196 MAPBGA |
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