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72SD3232BRPFH Datasheet(PDF) 2 Page - Maxwell Technologies |
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72SD3232BRPFH Datasheet(HTML) 2 Page - Maxwell Technologies |
2 / 41 page 72SD3232B 2 All data sheets are subject to change without notice ©2008 Maxwell Technologies All rights reserved. 1 Gbit(8-Meg X 32-Bit X 4-Banks) SDRAM 06.11.08 Rev 1 Pinout Description Pin Descriptions Pin Name Function A0 to A12 Address Input BA0, BA1 Row Address A0 to A12 Column Address A0 to A9 Bank Select Address BA0/BA1 (BS) DQ0 to DQ7 Data-Input/Output - Layer 1 DQ8 to DQ15 Data-Input/Output - Layer 2 DQ16 to DQ23 Data-Input/Output - Layer 3 DQ24 to DQ32 Data-Input/Output - Layer 4 CS\ Chip Select RAS\ Row Address Strobe CAS\ Column Address Strobe WE\ Write Enable DQM 1 Input/Output Mask - Layer 1 DQM 2 Input/Output Mask - Layer 2 DQM 3 Input/Output Mask - Layer 3 DQM 4 Input/Output Mask - Layer 4 CLK1 Clock Input - Layer 1 & 3 CLK2 Clock Input - Layer 2 & 4 CKE Clock Enable Vcc Power for internal circuits Vss Ground for internal circuits VccQ Power for DQ circuits VssQ Ground for DQ circuits NC No Connection |
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