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LMK04816BISQX Datasheet(PDF) 11 Page - Texas Instruments |
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LMK04816BISQX Datasheet(HTML) 11 Page - Texas Instruments |
11 / 123 page LMK04816 www.ti.com SNAS597B – JULY 2012 – REVISED APRIL 2013 3.4 Electrical Characteristics (3.15 V ≤ VCC ≤ 3.45 V, -40 °C ≤ TA ≤ 85 °C. Typical values represent most likely parametric norms at VCC = 3.3 V, TA = 25 °C, at the Recommended Operating Conditions at the time of product characterization and are not ensured.) Symbol Parameter Conditions Min Typ Max Units Current Consumption ICC_PD Power Down Supply Current 1 3 mA All clock delays disabled, Supply Current with all clocks enabled CLKoutX_Y_DIV = 1045, ICC_CLKS 505 590 mA (1) CLKoutX_TYPE = 1 (LVDS), PLL1 and PLL2 locked. CLKin0/0*, CLKin1/1*, and CLKin2/2* Input Clock Specifications fCLKin Clock Input Frequency (2) 0.001 500 MHz Clock Input Slew Rate SLEWCLKin 20% to 80% 0.15 0.5 V/ns (3) (4) VIDCLKin 0.25 1.55 |V| AC coupled Clock Input CLKinX_BUF_TYPE = 0 (Bipolar) VSSCLKin 0.5 3.1 Vpp Differential Input Voltage (5) VIDCLKin 0.25 1.55 |V| AC coupled Figure 4-2 CLKinX_BUF_TYPE = 1 (MOS) VSSCLKin 0.5 3.1 Vpp AC coupled to CLKinX; CLKinX* AC coupled to Ground 0.25 2.4 Vpp CLKinX_BUF_TYPE = 0 (Bipolar) Clock Input VCLKin Single-ended Input Voltage (3) AC coupled to CLKinX; CLKinX* AC coupled to Ground 0.25 2.4 Vpp CLKinX_BUF_TYPE = 1 (MOS) DC offset voltage between VCLKin0-offset CLKin0/CLKin0* 20 mV CLKin0* - CLKin0 DC offset voltage between Each pin AC coupled VCLKin1-offset CLKin1/CLKin1* 0 mV CLKin0_BUF_TYPE = 0 (Bipolar) CLKin1* - CLKin1 DC offset voltage between VCLKin2-offset CLKin2/CLKin2* 20 mV CLKin2*- CLKin2 DC offset voltage between Each pin AC coupled VCLKinX-offset CLKinX/CLKinX* 55 mV CLKinX_BUF_TYPE = 1 (MOS) CLKinX* - CLKinX VCLKin-VIH High input voltage DC coupled to CLKinX; CLKinX* AC 2.0 VCC V coupled to Ground VCLKin-VIL Low input voltage 0.0 0.4 V CLKinX_BUF_TYPE = 1 (MOS) FBCLKin/FBCLKin* and Fin/Fin* Input Specifications AC coupled fFBCLKin Clock Input Frequency (3) (CLKinX_BUF_TYPE = 0) 0.001 1000 MHz MODE = 2 or 8; FEEDBACK_MUX = 6 AC coupled fFin Clock Input Frequency (3) (CLKinX_BUF_TYPE = 0) 0.001 3100 MHz MODE = 3 or 11 Single Ended AC coupled; VFBCLKin/Fin 0.25 2.0 Vpp Clock Input Voltage (3) (CLKinX_BUF_TYPE = 0) (1) Load conditions for output clocks: LVDS: 100 Ω differential. See applications section Current Consumption/Power Dissipation Calculations for Icc for specific part configuration and how to calculate Icc for a specific design. (2) CLKin0, CLKin1, and CLKin2 maximum is ensured by characterization, production tested at 200 MHz. (3) Ensured by characterization. (4) In order to meet the jitter performance listed in the subsequent sections of this data sheet, the minimum recommended slew rate for all input clocks is 0.5 V/ns. This is especially true for single-ended clocks. Phase noise performance will begin to degrade as the clock input slew rate is reduced. However, the device will function at slew rates down to the minimum listed. When compared to single-ended clocks, differential clocks (LVDS, LVPECL) will be less susceptible to degradation in phase noise performance at lower slew rates due to their common mode noise rejection. However, it is also recommended to use the highest possible slew rate for differential clocks to achieve optimal phase noise performance at the device outputs. (5) See Section 4.2 for definition of VID and VOD voltages. Copyright © 2012–2013, Texas Instruments Incorporated Electrical Specifications 11 Submit Documentation Feedback Product Folder Links: LMK04816 |
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