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FOD060L Datasheet(PDF) 4 Page - Fairchild Semiconductor

Part # FOD060L
Description  3.3V/5V High Speed-10 MBit/s Logic Gate Optocouplers
Download  19 Pages
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Manufacturer  FAIRCHILD [Fairchild Semiconductor]
Direct Link  http://www.fairchildsemi.com
Logo FAIRCHILD - Fairchild Semiconductor

FOD060L Datasheet(HTML) 4 Page - Fairchild Semiconductor

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©2008 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FOD060L, FOD260L Rev. 1.0.5
4
Transfer Characteristics (T
A = -40°C to +85°C Unless otherwise specified. Typical value is measured at
TA = 25°C and VCC = 3.3V)
Isolation Characteristics (T
A = -40°C to +85°C Unless otherwise specified. Typical value is measured at
TA = 25°C and VCC = 3.3V)
Notes
1. The VCC supply to each optoisolator must be bypassed by a 0.1µF capacitor or larger. This can be either a ceramic
or solid tantalum capacitor with good high frequency characteristic and should be connected as close as possible
to the package VCC and GND pins of each device.
2. Enable Input – No pull up resistor required as the device has an internal pull up resistor.
3. tPLH – Propagation delay is measured from the 3.75 mA level on the HIGH to LOW transition of the input current
pulse to the 1.5V level on the LOW to HIGH transition of the output voltage pulse.
4. tPHL – Propagation delay is measured from the 3.75 mA level on the LOW to HIGH transition of the input current
pulse to the 1.5V level on the HIGH to LOW transition of the output voltage pulse.
5. tPSK is the worst case difference between tPHL and tPLH for any devices at the stated test conditions.
6. tr – Rise time is measured from the 90% to the 10% levels on the LOW to HIGH transition of the output pulse.
7. tf – Fall time is measured from the 10% to the 90% levels on the HIGH to LOW transition of the output pulse.
8. tELH – Enable input propagation delay is measured from the 1.5V level on the HIGH to LOW transition of the input
voltage pulse to the 1.5V level on the LOW to HIGH transition of the output voltage pulse.
9. tEHL – Enable input propagation delay is measured from the 1.5V level on the LOW to HIGH transition of the input
voltage pulse to the 1.5V level on the HIGH to LOW transition of the output voltage pulse.
10. CMH – The maximum tolerable rate of rise of the common mode voltage to ensure the output will remain in the high
state (i.e., VOUT > 2.0 V). Measured in volts per microsecond (V/µs).
11. CML – The maximum tolerable rate of fall of the common mode voltage to ensure the output will remain in the low
output state (i.e., VOUT < 0.8 V). Measured in volts per microsecond (V/µs).
12. Device considered a two-terminal device: Pins 1, 2, 3 and 4 shorted together, and Pins 5, 6, 7 and 8 shorted
together.
Symbol DC Characteristics
Test Conditions
Min.
Typ.
Max.
Unit
IOH
High Level Output Current
IF = 250 µA, VCC = 3.3 V, VO = 3.3 V,
VE = 2.0 V (Note 2)
0.01
50
µA
VOL
Low Level Output Voltage
VCC = 3.3 V, IF = 5 mA, IOL = 13 mA,
VE = 2.0 V (Note 2)
0.3
0.6
V
IFT
Input Threshold Current
VCC = 3.3 V, VO = 0.6 V, IOL = 13 mA,
VE = 2.0 V (Note 2)
15
mA
Symbol
Characteristics
Test Conditions
Min.
Typ.
Max.
Unit
II-O
Input-Output
Insulation Leakage Current
Relative humidity = 45%,
TA = 25°C, t = 5 s,
VI-O = 3000 VDC (Note 12)
1.0
µA
VISO
Withstand Insulation Test
Voltage
FOD060L
FOD260L
IIO ≤ 2 µA, RH < 50%,
TA = 25°C, t = 1 min.(Note 12)
3750
VRMS
5000
RI-O
Resistance (Input to Output)
VI-O = 500 V (Note 12)
1012
CI-O
Capacitance (Input to Output) f = 1 MHz (Note 12)
0.6
pF


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