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TPS2541RTER Datasheet(PDF) 4 Page - Texas Instruments

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Part # TPS2541RTER
Description  USB Charging Port Power Switch and Controller
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TPS2541RTER Datasheet(HTML) 4 Page - Texas Instruments

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TPS2540, TPS2540A
TPS2541, TPS2541A
SLVSAG2C
– OCTOBER 2010 – REVISED OCTOBER 2011
www.ti.com
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
NOM
MAX
UNIT
VIN
Input voltage, IN
4.5
5.5
Input voltage, logic-level inputs,
(CTL1, CTL2, CTL3, EN (TPS2540/40A), DSC (TPS2541/41A),
0
5.5
V
ILIM_SEL)
Input voltage, data line inputs, (DP_IN, DM_IN, DP_OUT, DM_OUT)
5.5
Continuous current, data line inputs,
±30
(SDP or CDP mode, DP_IN to DP_OUT or DM_IN to DM_OUT )
mA
Continuous current, data line inputs, (BC1.2 DCP mode, DP_IN to
±10
DM_IN)
IOUT
Continuous output current, OUT
0
2.5
A
RILIMx
Current-limit set resistors, (ILIM0 to GND, ILIM1 to GND)
16.9
750
k
Ω
TJ
Operating virtual junction temperature
-40
125
°C
THERMAL INFORMATION
TPS2540
TPS2540A
TPS2541
THERMAL METRIC(1)
UNITS
TPS2541A
RTE
16 PINS
θJA
Junction-to-ambient thermal resistance(2)
53.4
θJCtop
Junction-to-case (top) thermal resistance(3)
51.4
θJB
Junction-to-board thermal resistance(4)
17.2
°C/W
ψJT
Junction-to-top characterization parameter(5)
3.7
ψJB
Junction-to-board characterization parameter(6)
20.7
θJCbot
Junction-to-case (bottom) thermal resistance(7)
3.9
(1)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2)
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3)
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4)
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5)
The junction-to-top characterization parameter,
ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining
θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6)
The junction-to-board characterization parameter,
ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining
θJA , using a procedure described in JESD51-2a (sections 6 and 7).
(7)
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
4
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Copyright
© 2010–2011, Texas Instruments Incorporated
Product Folder Link(s): TPS2540, TPS2540A TPS2541, TPS2541A


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