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TPS53114 Datasheet(PDF) 2 Page - Texas Instruments |
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TPS53114 Datasheet(HTML) 2 Page - Texas Instruments |
2 / 27 page TPS53114PWP (TSSOP16) SW DRVL DRVH VBST EN VO VFB GND VREG5 TRIP PGND C3 C1 10uFx2 L1 R2 R1 C2 0.1uF Q1 Q2 VO1 C5 4.7uF C6 1uF R3 1 16 10 13 14 15 8 11 12 4 6 7 VIN FSEL V5FILT 9 CER 5 3 SS VIN 2 C4 VIN C7 THERMAL PAD SGND SGND SGND SGND PGND PGND TPS53114PW (TSSOP16) SW DRVL DRVH VBST EN VO VFB GND VREG5 TRIP PGND C3 C1 10uFx2 L1 R2 R1 C2 0.1uF Q1 Q2 VO1 C5 4.7uF C6 1uF R3 1 16 10 13 14 15 8 11 12 4 6 7 VIN FSEL V5FILT 9 CER 5 3 SS VIN 2 C4 VI N C7 SG ND SG ND SG ND SGND PG ND PG ND TPS53114 SLVS887B – APRIL 2009 – REVISED OCTOBER 2010 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. TYPICAL APPLICATION CIRCUITS Figure 1. HTSSOP Figure 2. TSSOP 2 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s) :TPS53114 |
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