TPS54611Q1,TPS54612Q1

TPS54613Q1,TPS54614Q1

TPS54615Q1,TPS54616Q1

SGLS266G − OCTOBER 2004 − REVISED JUNE 2008

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3

Terminal Functions

TERMINAL

DESCRIPTION

NAME

NO.

DESCRIPTION

AGND

1

Analog ground. Return for slow-start capacitor, VBIAS capacitor, RT resistor FSEL. Make PowerPAD connection to AGND.

BOOT

5

Bootstrap input. A 0.022-

µF to 0.1-µF low-ESR capacitor connected from BOOT to PH generates a floating drive for the

high-set FET driver.

NC

3

No connection

PGND

15−19

Power ground. High current return for the low-side driver and power MOSFET. Connect PGND with large copper areas to

the input and output supply returns and negative terminals of the input and output capacitors.

PH

6−14

Phase input/output. Junction of the internal high-side and low-side power MOSFETs, and output inductor.

PWRGD

4

Power good open drain output. High-Z when VSENSE

≥ 90% Vref, otherwise PWRGD is low. Note that output is low when

SS/ENA is low or internal shutdown signal active.

RT

28

Frequency setting resistor input. Connect a resistor from RT to AGND to set the switching frequency.

SS/ENA

26

Slow-start/enable input/output. Dual function pin which provides logic input to enable/disable device operation and

capacitor input to externally set the start-up time.

FSEL

27

Frequency select input. Provides logic input to select between two internally set switching frequencies.

VBIAS

25

Internal bias regulator output. Supplies regulated voltage to internal circuitry. Bypass VBIAS pin to AGND pin with a high

quality, low-ESR 0.1-

µF to 1-µF ceramic capacitor.

VIN

20−24

Input supply for the power MOSFET switches and internal bias regulator. Bypass VIN pins to PGND pins close to device

package with a high quality, low-ESR 1-

µF to 10-µF ceramic capacitor.

VSENSE

2

Error amplifier inverting input. Connect directly to output voltage sense point.

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range unless otherwise noted(1)

VIN, SS/ENA, FSEL

−0.3 V to 7 V

VI

Input voltage range

RT

−0.3 V to 6 V

VI

Input voltage range

VSENSE

−0.3 V to 4 V

BOOT

−0.3 V to 17 V

VO

Output voltage range

VBIAS, PWRGD

−0.3 V to 7 V

VO

Output voltage range

PH

−0.6 V to 10 V

IO

Source current

PH

Internally Limited

IO

Source current

VBIAS

6 mA

IS

Sink current

PH

12 A

IS

Sink current

SS/ENA, PWRGD

10 mA

Voltage differential

AGND to PGND

±0.3 V

Continuous power dissipation

See Power Dissipation Rating Table

TJ

Operating virtual junction temperature range

−40

°C to 150°C

Tstg

Storage temperature

−65

°C to 150°C

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds

300

°C

(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.