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ADM6824TYRJZ-R7 Datasheet(PDF) 9 Page - Analog Devices |
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ADM6824TYRJZ-R7 Datasheet(HTML) 9 Page - Analog Devices |
9 / 12 page ADM6821/ADM6822/ADM6823/ADM6824/ADM6825 Rev. 0 | Page 9 of 12 CIRCUIT DESCRIPTION The ADM682x provide microprocessor supply voltage supervision by controlling the microprocessor’s reset input. Code execution errors are avoided during power-up, power- down, and brownout conditions by asserting a reset signal when the supply voltage is below a preset threshold. In addition, the ADM682x allow supply voltage stabilization with a fixed timeout before the reset deasserts after the supply voltage rises above the threshold. Problems with microprocessor code execution can be monitored and corrected with a watchdog timer (ADM6821/ ADM6822/ADM6823/ADM6824). When watchdog strobe instructions are included in microprocessor code, a watchdog timer detects if the microprocessor code breaks down or becomes stuck in an infinite loop. If this happens, the watchdog timer asserts a reset pulse, which restarts the microprocessor in a known state. If the user detects a problem with the system’s operation, a manual reset input is available (ADM6821/ADM6822/ ADM6823/ADM6825) to reset the microprocessor by means of an external push-button, for example. RESET OUTPUT The ADM6821 features an active-high push-pull reset output. The ADM6822 features an active-low open-drain reset output, while the ADM6823 features an active-low push-pull output. The ADM6824/ADM6825 feature dual active-low and active- high push-pull reset outputs. For active-low and active-high outputs, the reset signal is guaranteed to be logic low and logic high, respectively, for VCC down to 1 V. The reset output is asserted when VCC is below the reset threshold (VTH), when MR is driven low, or when WDI is not serviced within the watchdog timeout period (tWD). Reset remains asserted for the duration of the reset active timeout period (tRP) after VCC rises above the reset threshold, after MR transitions from low to high, or after the watchdog timer times out. Figure 14 shows the reset outputs. VCC 1V VCC 0V VCC 0V VTH VTH 0V VCC RESET RESET tRD tRD 1V tRP tRP Figure 14. Reset Timing Diagram MANUAL RESET INPUT The ADM6821/ADM6822/ADM6823/ADM6825 feature a manual reset input (MR), which, when driven low, asserts the reset output. When MR transitions from low to high, reset remains asserted for the duration of the reset active timeout period before deasserting. The MR input has a 50 kΩ internal pull-up so that the input is always high when unconnected. An external push-button switch can be connected between MR and ground so that the user can generate a reset. Debounce circuitry is integrated on-chip for this purpose. Noise immunity is provided on the MR input, and fast, negative-going transients of up to 100 ns (typ) are ignored. A 0.1 μF capacitor between MR and ground provides additional noise immunity. WATCHDOG INPUT The ADM6821/ADM6822/ADM6823/ADM6824 feature a watchdog timer, which monitors microprocessor activity. A timer circuit is cleared with every low-to-high or high-to-low logic transition on the watchdog input pin (WDI), which detects pulses as short as 50 ns. If the timer counts through the preset watchdog timeout period (tWD), reset is asserted. The microprocessor is required to toggle the WDI pin to avoid being reset. Failure of the microprocessor to toggle WDI within the timeout period therefore indicates a code execution error, and the reset pulse generated restarts the microprocessor in a known state. In addition to logic transitions on WDI, the watchdog timer is also cleared by a reset assertion due to an undervoltage condi- tion on VCC or MR being pulled low. When reset is asserted, the watchdog timer is cleared and does not begin counting again until reset deassserts. The watchdog timer can be disabled by leaving WDI floating or by three-stating the WDI driver. VCC 1V VCC 0V VCC 0V VTH 0V VCC WDI RESET tRP tRD tWD Figure 15. Watchdog Timing Diagram |
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