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AOZ5066QI Datasheet(PDF) 9 Page - Alpha & Omega Semiconductors |
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AOZ5066QI Datasheet(HTML) 9 Page - Alpha & Omega Semiconductors |
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9 / 16 page  Rev. 1.0 August 2013 www.aosmd.com Page 9 of 16 AOZ5066 Timing Diagram Figure 13. Timing Diagram Application Information AOZ5066QI and AOZ5066QI-01 are fully integrated power modules designed to work over an input voltage range of 4.5V to 25V with 5V supplies for gate drive and internal control circuits. A number of features are provided making the AOZ5066QI a highly versatile power module. High side and low side power MOSFETs are combined in one package with the pin outs optimized for power routing with minimum parasitic inductances. The MOSFETs are individually tailored for efficient operation as either high side or low side switches in a low duty cycle synchronous buck converter. A high current driver is also included in the package which minimizes the gate drive loop and results in extremely fast switching. The modules are fully compatible with Intel DrMOS specification Rev 4.0 in form fit and function. Powering the Module and the Gate Drives An external supply VDRV of 5V is required for driving the MOSFETs. The MOSFETs are designed with low gate thresholds so that lower drive voltage can be used to reduce the switching and drive losses without compromising the conduction losses. The control logic supply VCIN can be derived from the gate drive supply VDRV through an RC filter to bypass the switching noise. See Figure 14 for recommended gate drive supply connections. The gate driver is capable of supplying several amperes of peak current into the LS FET to achieve extremely fast switching. A ceramic bypass capacitor of 1F or higher is recommended from VDRV to CGND. The boost supply for driving the high side MOSFET is generated by connecting a small capacitor between BOOT pin and the switching node VSWH. It is recommended that this capacitor Cboot be connected as close as possible to the device across pins 4 and 7. Boost diode is integrated into the package. Rboot is an optional resistor used by designers to slow down the turn on speed of the high side MOSFET. The value is a compromise between the need to keep both the switching time and VSWH node spikes as low as possible and is typically 1 to 5 Undervoltage Lockout and Enable VCIN is monitored for UVLO conditions and both outputs are actively held low unless adequate gate supply is available. The undervoltage lockout is set at 3.5V with a 550mV hysteresis. Since the PWM control signals are provided typically from an external controller or a digital processor extra care must be taken during start up. The AOZ5066QI must be powered up and enabled before the PWM input is applied. It should be ensured that PWM signal goes through a proper soft start sequence to minimise inrush current in the converter during start up. Powering the module with a full duty cycle PWM signal already applied may lead to a number of undesirable consequences as explained below. Outputs can also be turned off through the DISB# pin. When this input is grounded the drivers are disabled and held active low. The module is in standby mode with low quiescent current of less than 75A. PWM GH GL tPDLL tPDLU tTSSHD tTSSHD tPTS tPTS tPDHL tPDHU PWM Tri State Band |
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