 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
AOZ3015PI Datasheet(PDF) 10 Page - Alpha & Omega Semiconductors |
|
||||||||||||||||||||||||||||||
AOZ3015PI Datasheet(HTML) 10 Page - Alpha & Omega Semiconductors |
|
|
10 / 13 page  AOZ3015PI Rev. 2.0 July 2013 www.aosmd.com Page 10 of 13 Thermal Management and Layout Considerations In the AOZ3015PI buck regulator circuit, high pulsing current flows through two circuit loops. The first loop starts from the input capacitors, to the VIN pin, to the LX pad, to the filter inductor, to the output capacitor and load, and then returns to the input capacitor through ground. Current flows in the first loop when the high side switch is on. The second loop starts from the inductor, to the output capacitors and load, to the low side NMOSFET. Current flows in the second loop when the low side NMOSFET is on. In PCB layout, minimizing the area of the two loops will reduce the noise of the circuit and improves efficiency. A ground plane is strongly recommended to connect the input capacitor, the output capacitor, and the PGND pin of the AOZ3015PI. In the AOZ3015PI buck regulator circuit, the major power dissipating components are the AOZ3015PI and the output inductor. The total power dissipation of converter circuit can be measured by input power minus output power: The power dissipation of the inductor can be approximately calculated by the output current and DCR value of the inductor: The actual junction temperature can be calculated by the power dissipation in the AOZ3015PI and the thermal impedance from junction to ambient: The maximum junction temperature of the AOZ3015PI is 150 ºC, which limits the maximum load current capability. The thermal performance of the AOZ3015PI is strongly affected by the PCB layout. Care should be taken during the design process to ensure that the IC will operate under the recommended environmental conditions. Layout Considerations The AOZ3015PI is an exposed pad SO-8 package. Several layout tips are listed for the best electric and thermal performance. 1. The exposed pad (LX) is connected to the internal PFET and NFET drains. Connected a large copper plane to the LX pin to help thermal dissipation. 2. Do not use a thermal relief connection to the VIN pin or the PGND pin. Pour a maximized copper area to the PGND pin and the VIN pin to help thermal dissipation. 3. The input capacitor should be connected as close as possible to the VIN pin and the PGND pin. 4. A ground plane is preferred. If a ground plane is not used, separate PGND from AGND and only connect them at one point to avoid the PGND pin noise coupling to the AGND pin. 5. Make the current trace from the LX pad to L to Co to the PGND as short as possible. 6. Pour copper plane on all unused board area and connect it to stable DC nodes, like VIN, GND or VOUT. 7. Keep sensitive signal trace away from the LX pad. P total_loss V IN I IN V O I O – = P inductor_loss I O 2 R inductor 1.1 = T junction P total_loss Pinductor_loss – JA = |
Similar Part No. - AOZ3015PI |
|
Similar Description - AOZ3015PI |
|
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.NET |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
